1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * https://beagley-ai.org/ 4 * 5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-j722s.dtsi" 14 15/ { 16 compatible = "beagle,am67a-beagley-ai", "ti,j722s"; 17 model = "BeagleBoard.org BeagleY-AI"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial2 = &main_uart0; 22 mmc1 = &sdhci1; 23 rtc0 = &rtc; 24 }; 25 26 chosen { 27 stdout-path = &main_uart0; 28 }; 29 30 memory@80000000 { 31 /* 4G RAM */ 32 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 33 <0x00000008 0x80000000 0x00000000 0x80000000>; 34 device_type = "memory"; 35 bootph-pre-ram; 36 }; 37 38 reserved_memory: reserved-memory { 39 #address-cells = <2>; 40 #size-cells = <2>; 41 ranges; 42 43 secure_tfa_ddr: tfa@9e780000 { 44 reg = <0x00 0x9e780000 0x00 0x80000>; 45 no-map; 46 }; 47 48 secure_ddr: optee@9e800000 { 49 reg = <0x00 0x9e800000 0x00 0x01800000>; 50 no-map; 51 }; 52 53 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa0000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa0100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa1000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa1100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa2000000 0x00 0x100000>; 80 no-map; 81 }; 82 83 main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa2100000 0x00 0xf00000>; 86 no-map; 87 }; 88 89 c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa3000000 0x00 0x100000>; 92 no-map; 93 }; 94 95 c7x_0_memory_region: c7x-memory@a3100000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa3100000 0x00 0xf00000>; 98 no-map; 99 }; 100 101 c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { 102 compatible = "shared-dma-pool"; 103 reg = <0x00 0xa4000000 0x00 0x100000>; 104 no-map; 105 }; 106 107 c7x_1_memory_region: c7x-memory@a4100000 { 108 compatible = "shared-dma-pool"; 109 reg = <0x00 0xa4100000 0x00 0xf00000>; 110 no-map; 111 }; 112 113 rtos_ipc_memory_region: ipc-memories@a5000000 { 114 reg = <0x00 0xa5000000 0x00 0x1c00000>; 115 alignment = <0x1000>; 116 no-map; 117 }; 118 }; 119 120 vsys_5v0: regulator-1 { 121 compatible = "regulator-fixed"; 122 regulator-name = "vsys_5v0"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 regulator-always-on; 126 regulator-boot-on; 127 bootph-all; 128 }; 129 130 vdd_3v3: regulator-2 { 131 compatible = "regulator-fixed"; 132 regulator-name = "vdd_3v3"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 vin-supply = <&vsys_5v0>; 136 regulator-always-on; 137 regulator-boot-on; 138 }; 139 140 vdd_mmc1: regulator-3 { 141 compatible = "regulator-fixed"; 142 regulator-name = "vdd_mmc1"; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&vdd_3v3_sd_pins_default>; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 regulator-boot-on; 148 enable-active-high; 149 gpio = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; 150 bootph-all; 151 }; 152 153 vdd_sd_dv: regulator-4 { 154 compatible = "regulator-gpio"; 155 regulator-name = "tlv71033"; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&vdd_sd_dv_pins_default>; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <3300000>; 160 regulator-boot-on; 161 vin-supply = <&vsys_5v0>; 162 gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; 163 states = <1800000 0x0>, 164 <3300000 0x1>; 165 bootph-all; 166 }; 167 168 vsys_io_1v8: regulator-5 { 169 compatible = "regulator-fixed"; 170 regulator-name = "vsys_io_1v8"; 171 regulator-min-microvolt = <1800000>; 172 regulator-max-microvolt = <1800000>; 173 regulator-always-on; 174 regulator-boot-on; 175 }; 176 177 vsys_io_1v2: regulator-6 { 178 compatible = "regulator-fixed"; 179 regulator-name = "vsys_io_1v2"; 180 regulator-min-microvolt = <1200000>; 181 regulator-max-microvolt = <1200000>; 182 regulator-always-on; 183 regulator-boot-on; 184 }; 185 186 leds { 187 compatible = "gpio-leds"; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&led_pins_default>; 190 191 led-0 { 192 gpios = <&main_gpio0 11 GPIO_ACTIVE_LOW>; 193 default-state = "off"; 194 }; 195 196 led-1 { 197 gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 198 linux,default-trigger = "heartbeat"; 199 function = LED_FUNCTION_HEARTBEAT; 200 default-state = "on"; 201 }; 202 }; 203}; 204 205&main_pmx0 { 206 main_i2c0_pins_default: main-i2c0-default-pins { 207 pinctrl-single,pins = < 208 J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ 209 J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ 210 >; 211 bootph-all; 212 }; 213 214 main_uart0_pins_default: main-uart0-default-pins { 215 pinctrl-single,pins = < 216 J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ 217 J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ 218 >; 219 bootph-all; 220 }; 221 222 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 223 pinctrl-single,pins = < 224 J722S_IOPAD(0x0244, PIN_OUTPUT, 7) /* (A24) MMC1_SDWP.GPIO1_49 */ 225 >; 226 bootph-all; 227 }; 228 229 main_mmc1_pins_default: main-mmc1-default-pins { 230 pinctrl-single,pins = < 231 J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ 232 J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ 233 J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ 234 J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ 235 J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ 236 J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ 237 J722S_IOPAD(0x0240, PIN_INPUT, 7) /* (B24) MMC1_SDCD.GPIO1_48 */ 238 >; 239 bootph-all; 240 }; 241 242 mdio_pins_default: mdio-default-pins { 243 pinctrl-single,pins = < 244 J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ 245 J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ 246 >; 247 }; 248 249 rgmii1_pins_default: rgmii1-default-pins { 250 pinctrl-single,pins = < 251 J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ 252 J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ 253 J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ 254 J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ 255 J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ 256 J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ 257 J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ 258 J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ 259 J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ 260 J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ 261 J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ 262 J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ 263 >; 264 }; 265 266 led_pins_default: led-default-pins { 267 pinctrl-single,pins = < 268 J722S_IOPAD(0x002c, PIN_OUTPUT, 7) /* (K26) OSPI0_CSn0.GPIO0_11 */ 269 J722S_IOPAD(0x0030, PIN_OUTPUT, 7) /* (K23) OSPI0_CSn1.GPIO0_12 */ 270 >; 271 }; 272 273 pmic_irq_pins_default: pmic-irq-default-pins { 274 pinctrl-single,pins = < 275 J722S_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B23) EXTINTn */ 276 >; 277 }; 278 279 vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { 280 pinctrl-single,pins = < 281 J722S_IOPAD(0x0254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ 282 >; 283 }; 284}; 285 286&cpsw3g { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&rgmii1_pins_default>; 289 status = "okay"; 290}; 291 292&cpsw3g_mdio { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&mdio_pins_default>; 295 status = "okay"; 296 297 cpsw3g_phy0: ethernet-phy@0 { 298 reg = <0>; 299 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 300 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 301 ti,min-output-impedance; 302 }; 303}; 304 305&cpsw_port1 { 306 phy-mode = "rgmii-rxid"; 307 phy-handle = <&cpsw3g_phy0>; 308 status = "okay"; 309}; 310 311&main_gpio1 { 312 bootph-all; 313 status = "okay"; 314}; 315 316&main_uart0 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&main_uart0_pins_default>; 319 bootph-all; 320 status = "okay"; 321}; 322 323&mcu_pmx0 { 324 wkup_uart0_pins_default: wkup-uart0-default-pins { 325 pinctrl-single,pins = < 326 J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ 327 J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ 328 J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ 329 J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ 330 >; 331 bootph-all; 332 }; 333 334 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 335 pinctrl-single,pins = < 336 J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ 337 J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ 338 >; 339 bootph-all; 340 }; 341}; 342 343&wkup_uart0 { 344 /* WKUP UART0 is used by Device Manager firmware */ 345 pinctrl-names = "default"; 346 pinctrl-0 = <&wkup_uart0_pins_default>; 347 bootph-all; 348 status = "reserved"; 349}; 350 351&wkup_i2c0 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&wkup_i2c0_pins_default>; 354 clock-frequency = <100000>; 355 bootph-all; 356 status = "okay"; 357 358 tps65219: pmic@30 { 359 compatible = "ti,tps65219"; 360 reg = <0x30>; 361 buck1-supply = <&vsys_5v0>; 362 buck2-supply = <&vsys_5v0>; 363 buck3-supply = <&vsys_5v0>; 364 ldo1-supply = <&vdd_3v3>; 365 ldo3-supply = <&vdd_3v3>; 366 ldo4-supply = <&vdd_3v3>; 367 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pmic_irq_pins_default>; 370 interrupt-parent = <&gic500>; 371 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-controller; 373 #interrupt-cells = <1>; 374 375 bootph-all; 376 system-power-controller; 377 ti,power-button; 378 379 regulators { 380 buck1_reg: buck1 { 381 regulator-name = "VDD_3V3"; 382 regulator-min-microvolt = <3300000>; 383 regulator-max-microvolt = <3300000>; 384 regulator-boot-on; 385 regulator-always-on; 386 }; 387 388 buck2_reg: buck2 { 389 regulator-name = "VDD_1V8"; 390 regulator-min-microvolt = <1800000>; 391 regulator-max-microvolt = <1800000>; 392 regulator-boot-on; 393 regulator-always-on; 394 }; 395 396 ldo1_reg: ldo1 { 397 regulator-name = "VDDSHV5_SDIO"; 398 regulator-min-microvolt = <3300000>; 399 regulator-max-microvolt = <3300000>; 400 regulator-allow-bypass; 401 regulator-boot-on; 402 regulator-always-on; 403 }; 404 405 ldo2_reg: ldo2 { 406 regulator-name = "VDD_1V2"; 407 regulator-min-microvolt = <1200000>; 408 regulator-max-microvolt = <1200000>; 409 regulator-boot-on; 410 regulator-always-on; 411 }; 412 413 ldo3_reg: ldo3 { 414 regulator-name = "VDDA_PHY_1V8"; 415 regulator-min-microvolt = <1800000>; 416 regulator-max-microvolt = <1800000>; 417 regulator-boot-on; 418 regulator-always-on; 419 }; 420 421 ldo4_reg: ldo4 { 422 regulator-name = "VDDA_PLL_1V8"; 423 regulator-min-microvolt = <1800000>; 424 regulator-max-microvolt = <1800000>; 425 regulator-boot-on; 426 regulator-always-on; 427 }; 428 }; 429 }; 430 431 eeprom@50 { 432 compatible = "atmel,24c32"; 433 reg = <0x50>; 434 }; 435 436 rtc: rtc@68 { 437 compatible = "dallas,ds1340"; 438 reg = <0x68>; 439 }; 440}; 441 442&sdhci1 { 443 /* SD/MMC */ 444 vmmc-supply = <&vdd_mmc1>; 445 vqmmc-supply = <&vdd_sd_dv>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&main_mmc1_pins_default>; 448 disable-wp; 449 cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; 450 cd-debounce-delay-ms = <100>; 451 bootph-all; 452 ti,fails-without-test-cd; 453 status = "okay"; 454}; 455 456&mailbox0_cluster0 { 457 status = "okay"; 458 459 mbox_wkup_r5_0: mbox-wkup-r5-0 { 460 ti,mbox-rx = <0 0 0>; 461 ti,mbox-tx = <1 0 0>; 462 }; 463}; 464 465&mailbox0_cluster1 { 466 status = "okay"; 467 468 mbox_mcu_r5_0: mbox-mcu-r5-0 { 469 ti,mbox-rx = <0 0 0>; 470 ti,mbox-tx = <1 0 0>; 471 }; 472}; 473 474&mailbox0_cluster2 { 475 status = "okay"; 476 477 mbox_c7x_0: mbox-c7x-0 { 478 ti,mbox-rx = <0 0 0>; 479 ti,mbox-tx = <1 0 0>; 480 }; 481}; 482 483&mailbox0_cluster3 { 484 status = "okay"; 485 486 mbox_main_r5_0: mbox-main-r5-0 { 487 ti,mbox-rx = <0 0 0>; 488 ti,mbox-tx = <1 0 0>; 489 }; 490 491 mbox_c7x_1: mbox-c7x-1 { 492 ti,mbox-rx = <2 0 0>; 493 ti,mbox-tx = <3 0 0>; 494 }; 495}; 496 497/* Timers are used by Remoteproc firmware */ 498&main_timer0 { 499 status = "reserved"; 500}; 501 502&main_timer1 { 503 status = "reserved"; 504}; 505 506&main_timer2 { 507 status = "reserved"; 508}; 509 510&wkup_r5fss0 { 511 status = "okay"; 512}; 513 514&wkup_r5fss0_core0 { 515 mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; 516 memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 517 <&wkup_r5fss0_core0_memory_region>; 518}; 519 520&mcu_r5fss0 { 521 status = "okay"; 522}; 523 524&mcu_r5fss0_core0 { 525 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; 526 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 527 <&mcu_r5fss0_core0_memory_region>; 528}; 529 530&main_r5fss0 { 531 status = "okay"; 532}; 533 534&main_r5fss0_core0 { 535 mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; 536 memory-region = <&main_r5fss0_core0_dma_memory_region>, 537 <&main_r5fss0_core0_memory_region>; 538}; 539 540&c7x_0 { 541 mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; 542 memory-region = <&c7x_0_dma_memory_region>, 543 <&c7x_0_memory_region>; 544 status = "okay"; 545}; 546 547&c7x_1 { 548 mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; 549 memory-region = <&c7x_1_dma_memory_region>, 550 <&c7x_1_memory_region>; 551 status = "okay"; 552}; 553