1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-am654.dtsi" 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/net/ti-dp83867.h> 11 12/ { 13 compatible = "ti,am654-evm", "ti,am654"; 14 model = "Texas Instruments AM654 Base Board"; 15 16 aliases { 17 serial0 = &wkup_uart0; 18 serial1 = &mcu_uart0; 19 serial2 = &main_uart0; 20 i2c0 = &wkup_i2c0; 21 i2c1 = &mcu_i2c0; 22 i2c2 = &main_i2c0; 23 i2c3 = &main_i2c1; 24 i2c4 = &main_i2c2; 25 ethernet0 = &cpsw_port1; 26 mmc0 = &sdhci0; 27 mmc1 = &sdhci1; 28 }; 29 30 chosen { 31 stdout-path = "serial2:115200n8"; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 bootph-all; 37 /* 4G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 39 <0x00000008 0x80000000 0x00000000 0x80000000>; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 secure_ddr: secure-ddr@9e800000 { 48 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ 49 alignment = <0x1000>; 50 no-map; 51 }; 52 53 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0 0xa0000000 0 0x100000>; 56 no-map; 57 }; 58 59 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0 0xa0100000 0 0xf00000>; 62 no-map; 63 }; 64 65 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0 0xa1000000 0 0x100000>; 68 no-map; 69 }; 70 71 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0 0xa1100000 0 0xf00000>; 74 no-map; 75 }; 76 77 rtos_ipc_memory_region: ipc-memories@a2000000 { 78 reg = <0x00 0xa2000000 0x00 0x00100000>; 79 alignment = <0x1000>; 80 no-map; 81 }; 82 }; 83 84 gpio-keys { 85 compatible = "gpio-keys"; 86 autorepeat; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&push_button_pins_default>; 89 90 switch-5 { 91 label = "GPIO Key USER1"; 92 linux,code = <BTN_0>; 93 gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; 94 }; 95 96 switch-6 { 97 label = "GPIO Key USER2"; 98 linux,code = <BTN_1>; 99 gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; 100 }; 101 }; 102 103 evm_12v0: regulator-0 { 104 /* main supply */ 105 compatible = "regulator-fixed"; 106 regulator-name = "evm_12v0"; 107 regulator-min-microvolt = <12000000>; 108 regulator-max-microvolt = <12000000>; 109 regulator-always-on; 110 regulator-boot-on; 111 }; 112 113 vcc3v3_io: regulator-1 { 114 /* Output of TPS54334 */ 115 compatible = "regulator-fixed"; 116 regulator-name = "vcc3v3_io"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 regulator-always-on; 120 regulator-boot-on; 121 vin-supply = <&evm_12v0>; 122 }; 123 124 vdd_mmc1_sd: regulator-2 { 125 compatible = "regulator-fixed"; 126 regulator-name = "vdd_mmc1_sd"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 regulator-boot-on; 130 enable-active-high; 131 vin-supply = <&vcc3v3_io>; 132 gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; 133 }; 134 135 vtt_supply: regulator-3 { 136 compatible = "regulator-fixed"; 137 regulator-name = "vtt"; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&ddr_vtt_pins_default>; 140 regulator-min-microvolt = <3300000>; 141 regulator-max-microvolt = <3300000>; 142 enable-active-high; 143 regulator-always-on; 144 regulator-boot-on; 145 vin-supply = <&vcc3v3_io>; 146 gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>; 147 bootph-all; 148 }; 149}; 150 151&wkup_pmx0 { 152 wkup_uart0_pins_default: wkup-uart0-default-pins { 153 pinctrl-single,pins = < 154 AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ 155 AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ 156 AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 157 AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ 158 >; 159 bootph-all; 160 }; 161 162 ddr_vtt_pins_default: ddr-vtt-default-pins { 163 pinctrl-single,pins = < 164 AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ 165 >; 166 bootph-all; 167 }; 168 169 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 170 pinctrl-single,pins = < 171 AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ 172 AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ 173 >; 174 bootph-all; 175 }; 176 177 push_button_pins_default: push-button-default-pins { 178 pinctrl-single,pins = < 179 AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ 180 AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ 181 >; 182 }; 183 184 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 185 pinctrl-single,pins = < 186 AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ 187 AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ 188 AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */ 189 AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */ 190 AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */ 191 AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */ 192 AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */ 193 AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */ 194 AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */ 195 AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */ 196 AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ 197 >; 198 bootph-all; 199 }; 200 201 wkup_pca554_default: wkup-pca554-default-pins { 202 pinctrl-single,pins = < 203 AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ 204 >; 205 }; 206 207 mcu_uart0_pins_default: mcu-uart0-default-pins { 208 pinctrl-single,pins = < 209 AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ 210 AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ 211 AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ 212 AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ 213 >; 214 bootph-all; 215 }; 216 217 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 218 pinctrl-single,pins = < 219 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ 220 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ 221 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ 222 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ 223 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ 224 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ 225 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ 226 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ 227 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ 228 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ 229 AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ 230 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ 231 >; 232 }; 233 234 mcu_mdio_pins_default: mcu-mdio1-default-pins { 235 pinctrl-single,pins = < 236 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 237 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 238 >; 239 }; 240 241 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 242 pinctrl-single,pins = < 243 AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */ 244 AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ 245 >; 246 }; 247}; 248 249&main_pmx0 { 250 main_uart0_pins_default: main-uart0-default-pins { 251 pinctrl-single,pins = < 252 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ 253 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ 254 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ 255 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ 256 >; 257 bootph-all; 258 }; 259 260 main_i2c2_pins_default: main-i2c2-default-pins { 261 pinctrl-single,pins = < 262 AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ 263 AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ 264 >; 265 }; 266 267 main_spi0_pins_default: main-spi0-default-pins { 268 pinctrl-single,pins = < 269 AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ 270 AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ 271 AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ 272 AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ 273 >; 274 }; 275 276 main_mmc0_pins_default: main-mmc0-default-pins { 277 pinctrl-single,pins = < 278 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ 279 AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ 280 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ 281 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ 282 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ 283 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ 284 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ 285 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ 286 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ 287 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ 288 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ 289 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ 290 >; 291 bootph-all; 292 }; 293 294 main_mmc1_pins_default: main-mmc1-default-pins { 295 pinctrl-single,pins = < 296 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ 297 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ 298 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ 299 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ 300 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ 301 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ 302 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ 303 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ 304 >; 305 bootph-all; 306 }; 307 308 usb1_pins_default: usb1-default-pins { 309 pinctrl-single,pins = < 310 AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ 311 >; 312 }; 313}; 314 315&main_pmx1 { 316 main_i2c0_pins_default: main-i2c0-default-pins { 317 pinctrl-single,pins = < 318 AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ 319 AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ 320 >; 321 }; 322 323 main_i2c1_pins_default: main-i2c1-default-pins { 324 pinctrl-single,pins = < 325 AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ 326 AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ 327 >; 328 }; 329 330 ecap0_pins_default: ecap0-default-pins { 331 pinctrl-single,pins = < 332 AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ 333 >; 334 }; 335}; 336 337&wkup_uart0 { 338 /* Wakeup UART is used by System firmware */ 339 status = "reserved"; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&wkup_uart0_pins_default>; 342}; 343 344&mcu_uart0 { 345 status = "okay"; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&mcu_uart0_pins_default>; 348}; 349 350&main_uart0 { 351 status = "okay"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&main_uart0_pins_default>; 354 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 355 bootph-all; 356}; 357 358&wkup_i2c0 { 359 status = "okay"; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&wkup_i2c0_pins_default>; 362 clock-frequency = <400000>; 363 364 eeprom@50 { 365 /* AT24CM01 */ 366 compatible = "atmel,24c1024"; 367 reg = <0x50>; 368 }; 369 370 vdd_mpu: regulator@60 { 371 compatible = "ti,tps62363"; 372 reg = <0x60>; 373 regulator-name = "VDD_MPU"; 374 regulator-min-microvolt = <500000>; 375 regulator-max-microvolt = <1770000>; 376 regulator-always-on; 377 regulator-boot-on; 378 ti,vsel0-state-high; 379 ti,vsel1-state-high; 380 ti,enable-vout-discharge; 381 bootph-all; 382 }; 383 384 gpio@38 { 385 compatible = "nxp,pca9554"; 386 reg = <0x38>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 }; 390 391 pca9554: gpio@39 { 392 compatible = "nxp,pca9554"; 393 reg = <0x39>; 394 gpio-controller; 395 #gpio-cells = <2>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&wkup_pca554_default>; 398 interrupt-parent = <&wkup_gpio0>; 399 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 400 interrupt-controller; 401 #interrupt-cells = <2>; 402 }; 403}; 404 405&mcu_i2c0 { 406 status = "okay"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&mcu_i2c0_pins_default>; 409 clock-frequency = <400000>; 410}; 411 412&main_i2c0 { 413 status = "okay"; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&main_i2c0_pins_default>; 416 clock-frequency = <400000>; 417 418 pca9555: gpio@21 { 419 compatible = "nxp,pca9555"; 420 reg = <0x21>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 }; 424}; 425 426&main_i2c1 { 427 status = "okay"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&main_i2c1_pins_default>; 430 clock-frequency = <400000>; 431}; 432 433&main_i2c2 { 434 status = "okay"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&main_i2c2_pins_default>; 437 clock-frequency = <400000>; 438}; 439 440&ecap0 { 441 status = "okay"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&ecap0_pins_default>; 444}; 445 446&main_spi0 { 447 status = "okay"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&main_spi0_pins_default>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 ti,pindir-d0-out-d1-in; 453 454 flash@0 { 455 compatible = "jedec,spi-nor"; 456 reg = <0x0>; 457 spi-tx-bus-width = <1>; 458 spi-rx-bus-width = <1>; 459 spi-max-frequency = <48000000>; 460 }; 461}; 462 463&sdhci0 { 464 status = "okay"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&main_mmc0_pins_default>; 467 bus-width = <8>; 468 non-removable; 469 ti,driver-strength-ohm = <50>; 470 bootph-all; 471}; 472 473/* 474 * Because of erratas i2025 and i2026 for silicon revision 1.0, the 475 * SD card interface might fail. Boards with sr1.0 are recommended to 476 * disable sdhci1 477 */ 478&sdhci1 { 479 status = "okay"; 480 vmmc-supply = <&vdd_mmc1_sd>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&main_mmc1_pins_default>; 483 ti,driver-strength-ohm = <50>; 484 disable-wp; 485 bootph-all; 486}; 487 488&usb1 { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&usb1_pins_default>; 491 dr_mode = "otg"; 492}; 493 494&dwc3_0 { 495 status = "disabled"; 496}; 497 498&usb0_phy { 499 status = "disabled"; 500}; 501 502&tscadc0 { 503 status = "okay"; 504 adc { 505 ti,adc-channels = <0 1 2 3 4 5 6 7>; 506 }; 507}; 508 509&tscadc1 { 510 status = "okay"; 511 adc { 512 ti,adc-channels = <0 1 2 3 4 5 6 7>; 513 }; 514}; 515 516&serdes0 { 517 status = "disabled"; 518}; 519 520&serdes1 { 521 status = "disabled"; 522}; 523 524&mailbox0_cluster0 { 525 status = "okay"; 526 interrupts = <436>; 527 528 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 529 ti,mbox-tx = <1 0 0>; 530 ti,mbox-rx = <0 0 0>; 531 }; 532}; 533 534&mailbox0_cluster1 { 535 status = "okay"; 536 interrupts = <432>; 537 538 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 539 ti,mbox-tx = <1 0 0>; 540 ti,mbox-rx = <0 0 0>; 541 }; 542}; 543 544&mcu_r5fss0_core0 { 545 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 546 <&mcu_r5fss0_core0_memory_region>; 547 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 548}; 549 550&mcu_r5fss0_core1 { 551 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 552 <&mcu_r5fss0_core1_memory_region>; 553 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; 554}; 555 556&ospi0 { 557 status = "okay"; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 560 561 flash@0 { 562 compatible = "jedec,spi-nor"; 563 reg = <0x0>; 564 spi-tx-bus-width = <8>; 565 spi-rx-bus-width = <8>; 566 spi-max-frequency = <25000000>; 567 cdns,tshsl-ns = <60>; 568 cdns,tsd2d-ns = <60>; 569 cdns,tchsh-ns = <60>; 570 cdns,tslch-ns = <60>; 571 cdns,read-delay = <0>; 572 573 partitions { 574 compatible = "fixed-partitions"; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 578 partition@0 { 579 label = "ospi.tiboot3"; 580 reg = <0x0 0x80000>; 581 }; 582 583 partition@80000 { 584 label = "ospi.tispl"; 585 reg = <0x80000 0x200000>; 586 }; 587 588 partition@280000 { 589 label = "ospi.u-boot"; 590 reg = <0x280000 0x400000>; 591 }; 592 593 partition@680000 { 594 label = "ospi.env"; 595 reg = <0x680000 0x20000>; 596 }; 597 598 partition@6a0000 { 599 label = "ospi.env.backup"; 600 reg = <0x6a0000 0x20000>; 601 }; 602 603 partition@6c0000 { 604 label = "ospi.sysfw"; 605 reg = <0x6c0000 0x100000>; 606 }; 607 608 partition@800000 { 609 label = "ospi.rootfs"; 610 reg = <0x800000 0x37c0000>; 611 }; 612 613 partition@3fe0000 { 614 label = "ospi.phypattern"; 615 reg = <0x3fe0000 0x20000>; 616 }; 617 }; 618 }; 619}; 620 621&mcu_cpsw { 622 pinctrl-names = "default"; 623 pinctrl-0 = <&mcu_cpsw_pins_default>; 624}; 625 626&davinci_mdio { 627 status = "okay"; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&mcu_mdio_pins_default>; 630 631 phy0: ethernet-phy@0 { 632 reg = <0>; 633 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 634 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 635 }; 636}; 637 638&cpsw_port1 { 639 phy-mode = "rgmii-rxid"; 640 phy-handle = <&phy0>; 641}; 642 643&dss { 644 status = "disabled"; 645}; 646 647&wkup_gpio0 { 648 bootph-all; 649}; 650