1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 dynamic-power-coefficient = <90>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP>; 51 next-level-cache = <&l2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP>; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cpu0_opp_table>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 next-level-cache = <&l2>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a35"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 cpu-idle-states = <&CPU_SLEEP>; 81 next-level-cache = <&l2>; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP: cpu-sleep { 88 compatible = "arm,idle-state"; 89 local-timer-stop; 90 arm,psci-suspend-param = <0x0010000>; 91 entry-latency-us = <120>; 92 exit-latency-us = <250>; 93 min-residency-us = <900>; 94 }; 95 }; 96 97 l2: l2-cache { 98 compatible = "cache"; 99 }; 100 }; 101 102 cpu0_opp_table: opp-table-0 { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 opp-408000000 { 107 opp-hz = /bits/ 64 <408000000>; 108 opp-microvolt = <950000 950000 1340000>; 109 clock-latency-ns = <40000>; 110 opp-suspend; 111 }; 112 opp-600000000 { 113 opp-hz = /bits/ 64 <600000000>; 114 opp-microvolt = <950000 950000 1340000>; 115 clock-latency-ns = <40000>; 116 }; 117 opp-816000000 { 118 opp-hz = /bits/ 64 <816000000>; 119 opp-microvolt = <1025000 1025000 1340000>; 120 clock-latency-ns = <40000>; 121 }; 122 opp-1008000000 { 123 opp-hz = /bits/ 64 <1008000000>; 124 opp-microvolt = <1125000 1125000 1340000>; 125 clock-latency-ns = <40000>; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a35-pmu"; 131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 mac_clkin: external-mac-clock { 139 compatible = "fixed-clock"; 140 clock-frequency = <50000000>; 141 clock-output-names = "mac_clkin"; 142 #clock-cells = <0>; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 156 }; 157 158 xin24m: xin24m { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <24000000>; 162 clock-output-names = "xin24m"; 163 }; 164 165 grf: grf@ff000000 { 166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 167 reg = <0x0 0xff000000 0x0 0x08000>; 168 169 reboot-mode { 170 compatible = "syscon-reboot-mode"; 171 offset = <0x500>; 172 mode-bootloader = <BOOT_BL_DOWNLOAD>; 173 mode-loader = <BOOT_BL_DOWNLOAD>; 174 mode-normal = <BOOT_NORMAL>; 175 mode-recovery = <BOOT_RECOVERY>; 176 mode-fastboot = <BOOT_FASTBOOT>; 177 }; 178 }; 179 180 usb2phy_grf: syscon@ff008000 { 181 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; 182 reg = <0x0 0xff008000 0x0 0x4000>; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 186 u2phy: usb2phy@100 { 187 compatible = "rockchip,rk3308-usb2phy"; 188 reg = <0x100 0x10>; 189 assigned-clocks = <&cru USB480M>; 190 assigned-clock-parents = <&u2phy>; 191 clocks = <&cru SCLK_USBPHY_REF>; 192 clock-names = "phyclk"; 193 clock-output-names = "usb480m_phy"; 194 #clock-cells = <0>; 195 status = "disabled"; 196 197 u2phy_otg: otg-port { 198 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-names = "otg-bvalid", "otg-id", 202 "linestate"; 203 #phy-cells = <0>; 204 status = "disabled"; 205 }; 206 207 u2phy_host: host-port { 208 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 209 interrupt-names = "linestate"; 210 #phy-cells = <0>; 211 status = "disabled"; 212 }; 213 }; 214 }; 215 216 detect_grf: syscon@ff00b000 { 217 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 218 reg = <0x0 0xff00b000 0x0 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 }; 222 223 core_grf: syscon@ff00c000 { 224 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 225 reg = <0x0 0xff00c000 0x0 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 }; 229 230 i2c0: i2c@ff040000 { 231 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 232 reg = <0x0 0xff040000 0x0 0x1000>; 233 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 234 clock-names = "i2c", "pclk"; 235 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&i2c0_xfer>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c1: i2c@ff050000 { 244 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 245 reg = <0x0 0xff050000 0x0 0x1000>; 246 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 247 clock-names = "i2c", "pclk"; 248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&i2c1_xfer>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 256 i2c2: i2c@ff060000 { 257 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 258 reg = <0x0 0xff060000 0x0 0x1000>; 259 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 260 clock-names = "i2c", "pclk"; 261 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c2_xfer>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 status = "disabled"; 267 }; 268 269 i2c3: i2c@ff070000 { 270 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 271 reg = <0x0 0xff070000 0x0 0x1000>; 272 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 273 clock-names = "i2c", "pclk"; 274 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2c3m0_xfer>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 wdt: watchdog@ff080000 { 283 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; 284 reg = <0x0 0xff080000 0x0 0x100>; 285 clocks = <&cru PCLK_WDT>; 286 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 287 status = "disabled"; 288 }; 289 290 uart0: serial@ff0a0000 { 291 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 292 reg = <0x0 0xff0a0000 0x0 0x100>; 293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 295 clock-names = "baudclk", "apb_pclk"; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 300 status = "disabled"; 301 }; 302 303 uart1: serial@ff0b0000 { 304 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 305 reg = <0x0 0xff0b0000 0x0 0x100>; 306 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 308 clock-names = "baudclk", "apb_pclk"; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 313 status = "disabled"; 314 }; 315 316 uart2: serial@ff0c0000 { 317 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 318 reg = <0x0 0xff0c0000 0x0 0x100>; 319 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 321 clock-names = "baudclk", "apb_pclk"; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&uart2m0_xfer>; 326 status = "disabled"; 327 }; 328 329 uart3: serial@ff0d0000 { 330 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 331 reg = <0x0 0xff0d0000 0x0 0x100>; 332 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 334 clock-names = "baudclk", "apb_pclk"; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&uart3_xfer>; 339 status = "disabled"; 340 }; 341 342 uart4: serial@ff0e0000 { 343 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 344 reg = <0x0 0xff0e0000 0x0 0x100>; 345 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 347 clock-names = "baudclk", "apb_pclk"; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 352 status = "disabled"; 353 }; 354 355 spi0: spi@ff120000 { 356 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 357 reg = <0x0 0xff120000 0x0 0x1000>; 358 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 362 clock-names = "spiclk", "apb_pclk"; 363 dmas = <&dmac0 0>, <&dmac0 1>; 364 dma-names = "tx", "rx"; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 367 status = "disabled"; 368 }; 369 370 spi1: spi@ff130000 { 371 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 372 reg = <0x0 0xff130000 0x0 0x1000>; 373 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 377 clock-names = "spiclk", "apb_pclk"; 378 dmas = <&dmac0 2>, <&dmac0 3>; 379 dma-names = "tx", "rx"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 382 status = "disabled"; 383 }; 384 385 spi2: spi@ff140000 { 386 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 387 reg = <0x0 0xff140000 0x0 0x1000>; 388 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 392 clock-names = "spiclk", "apb_pclk"; 393 dmas = <&dmac1 16>, <&dmac1 17>; 394 dma-names = "tx", "rx"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 397 status = "disabled"; 398 }; 399 400 pwm8: pwm@ff160000 { 401 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 402 reg = <0x0 0xff160000 0x0 0x10>; 403 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 404 clock-names = "pwm", "pclk"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pwm8_pin>; 407 #pwm-cells = <3>; 408 status = "disabled"; 409 }; 410 411 pwm9: pwm@ff160010 { 412 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 413 reg = <0x0 0xff160010 0x0 0x10>; 414 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 415 clock-names = "pwm", "pclk"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pwm9_pin>; 418 #pwm-cells = <3>; 419 status = "disabled"; 420 }; 421 422 pwm10: pwm@ff160020 { 423 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 424 reg = <0x0 0xff160020 0x0 0x10>; 425 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 426 clock-names = "pwm", "pclk"; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pwm10_pin>; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 pwm11: pwm@ff160030 { 434 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 435 reg = <0x0 0xff160030 0x0 0x10>; 436 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 437 clock-names = "pwm", "pclk"; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pwm11_pin>; 440 #pwm-cells = <3>; 441 status = "disabled"; 442 }; 443 444 pwm4: pwm@ff170000 { 445 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 446 reg = <0x0 0xff170000 0x0 0x10>; 447 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 448 clock-names = "pwm", "pclk"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pwm4_pin>; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 455 pwm5: pwm@ff170010 { 456 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 457 reg = <0x0 0xff170010 0x0 0x10>; 458 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 459 clock-names = "pwm", "pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm5_pin>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm6: pwm@ff170020 { 467 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff170020 0x0 0x10>; 469 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm6_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm7: pwm@ff170030 { 478 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff170030 0x0 0x10>; 480 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 481 clock-names = "pwm", "pclk"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pwm7_pin>; 484 #pwm-cells = <3>; 485 status = "disabled"; 486 }; 487 488 pwm0: pwm@ff180000 { 489 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff180000 0x0 0x10>; 491 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 492 clock-names = "pwm", "pclk"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pwm0_pin>; 495 #pwm-cells = <3>; 496 status = "disabled"; 497 }; 498 499 pwm1: pwm@ff180010 { 500 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 501 reg = <0x0 0xff180010 0x0 0x10>; 502 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 503 clock-names = "pwm", "pclk"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pwm1_pin>; 506 #pwm-cells = <3>; 507 status = "disabled"; 508 }; 509 510 pwm2: pwm@ff180020 { 511 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 512 reg = <0x0 0xff180020 0x0 0x10>; 513 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 514 clock-names = "pwm", "pclk"; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pwm2_pin>; 517 #pwm-cells = <3>; 518 status = "disabled"; 519 }; 520 521 pwm3: pwm@ff180030 { 522 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 523 reg = <0x0 0xff180030 0x0 0x10>; 524 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 525 clock-names = "pwm", "pclk"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pwm3_pin>; 528 #pwm-cells = <3>; 529 status = "disabled"; 530 }; 531 532 rktimer: rktimer@ff1a0000 { 533 compatible = "rockchip,rk3288-timer"; 534 reg = <0x0 0xff1a0000 0x0 0x20>; 535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 537 clock-names = "pclk", "timer"; 538 }; 539 540 saradc: saradc@ff1e0000 { 541 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 542 reg = <0x0 0xff1e0000 0x0 0x100>; 543 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 545 clock-names = "saradc", "apb_pclk"; 546 #io-channel-cells = <1>; 547 resets = <&cru SRST_SARADC_P>; 548 reset-names = "saradc-apb"; 549 status = "disabled"; 550 }; 551 552 dmac0: dma-controller@ff2c0000 { 553 compatible = "arm,pl330", "arm,primecell"; 554 reg = <0x0 0xff2c0000 0x0 0x4000>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 557 arm,pl330-periph-burst; 558 clocks = <&cru ACLK_DMAC0>; 559 clock-names = "apb_pclk"; 560 #dma-cells = <1>; 561 }; 562 563 dmac1: dma-controller@ff2d0000 { 564 compatible = "arm,pl330", "arm,primecell"; 565 reg = <0x0 0xff2d0000 0x0 0x4000>; 566 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 568 arm,pl330-periph-burst; 569 clocks = <&cru ACLK_DMAC1>; 570 clock-names = "apb_pclk"; 571 #dma-cells = <1>; 572 }; 573 574 i2s_2ch_0: i2s@ff350000 { 575 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 576 reg = <0x0 0xff350000 0x0 0x1000>; 577 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 579 clock-names = "i2s_clk", "i2s_hclk"; 580 dmas = <&dmac1 8>, <&dmac1 9>; 581 dma-names = "tx", "rx"; 582 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 583 reset-names = "reset-m", "reset-h"; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2s_2ch_0_sclk 586 &i2s_2ch_0_lrck 587 &i2s_2ch_0_sdi 588 &i2s_2ch_0_sdo>; 589 status = "disabled"; 590 }; 591 592 i2s_2ch_1: i2s@ff360000 { 593 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 594 reg = <0x0 0xff360000 0x0 0x1000>; 595 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 597 clock-names = "i2s_clk", "i2s_hclk"; 598 dmas = <&dmac1 11>; 599 dma-names = "rx"; 600 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 601 reset-names = "reset-m", "reset-h"; 602 status = "disabled"; 603 }; 604 605 spdif_tx: spdif-tx@ff3a0000 { 606 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 607 reg = <0x0 0xff3a0000 0x0 0x1000>; 608 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 610 clock-names = "mclk", "hclk"; 611 dmas = <&dmac1 13>; 612 dma-names = "tx"; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&spdif_out>; 615 status = "disabled"; 616 }; 617 618 usb20_otg: usb@ff400000 { 619 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 620 "snps,dwc2"; 621 reg = <0x0 0xff400000 0x0 0x40000>; 622 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cru HCLK_OTG>; 624 clock-names = "otg"; 625 dr_mode = "otg"; 626 g-np-tx-fifo-size = <16>; 627 g-rx-fifo-size = <280>; 628 g-tx-fifo-size = <256 128 128 64 32 16>; 629 phys = <&u2phy_otg>; 630 phy-names = "usb2-phy"; 631 status = "disabled"; 632 }; 633 634 usb_host_ehci: usb@ff440000 { 635 compatible = "generic-ehci"; 636 reg = <0x0 0xff440000 0x0 0x10000>; 637 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 639 phys = <&u2phy_host>; 640 phy-names = "usb"; 641 status = "disabled"; 642 }; 643 644 usb_host_ohci: usb@ff450000 { 645 compatible = "generic-ohci"; 646 reg = <0x0 0xff450000 0x0 0x10000>; 647 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 649 phys = <&u2phy_host>; 650 phy-names = "usb"; 651 status = "disabled"; 652 }; 653 654 sdmmc: mmc@ff480000 { 655 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 656 reg = <0x0 0xff480000 0x0 0x4000>; 657 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 658 bus-width = <4>; 659 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 660 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 661 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 662 fifo-depth = <0x100>; 663 max-frequency = <150000000>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 666 status = "disabled"; 667 }; 668 669 emmc: mmc@ff490000 { 670 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 671 reg = <0x0 0xff490000 0x0 0x4000>; 672 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 673 bus-width = <8>; 674 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 675 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 676 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 677 fifo-depth = <0x100>; 678 max-frequency = <150000000>; 679 status = "disabled"; 680 }; 681 682 sdio: mmc@ff4a0000 { 683 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 684 reg = <0x0 0xff4a0000 0x0 0x4000>; 685 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 686 bus-width = <4>; 687 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 688 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 689 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 690 fifo-depth = <0x100>; 691 max-frequency = <150000000>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 694 status = "disabled"; 695 }; 696 697 nfc: nand-controller@ff4b0000 { 698 compatible = "rockchip,rk3308-nfc", 699 "rockchip,rv1108-nfc"; 700 reg = <0x0 0xff4b0000 0x0 0x4000>; 701 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 703 clock-names = "ahb", "nfc"; 704 assigned-clocks = <&cru SCLK_NANDC>; 705 assigned-clock-rates = <150000000>; 706 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 707 &flash_rdn &flash_rdy &flash_wrn>; 708 pinctrl-names = "default"; 709 status = "disabled"; 710 }; 711 712 gmac: ethernet@ff4e0000 { 713 compatible = "rockchip,rk3308-gmac"; 714 reg = <0x0 0xff4e0000 0x0 0x10000>; 715 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 716 interrupt-names = "macirq"; 717 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 718 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 719 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 720 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 721 clock-names = "stmmaceth", "mac_clk_rx", 722 "mac_clk_tx", "clk_mac_ref", 723 "clk_mac_refout", "aclk_mac", 724 "pclk_mac", "clk_mac_speed"; 725 phy-mode = "rmii"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 728 resets = <&cru SRST_MAC_A>; 729 reset-names = "stmmaceth"; 730 rockchip,grf = <&grf>; 731 status = "disabled"; 732 }; 733 734 sfc: spi@ff4c0000 { 735 compatible = "rockchip,sfc"; 736 reg = <0x0 0xff4c0000 0x0 0x4000>; 737 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 739 clock-names = "clk_sfc", "hclk_sfc"; 740 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 741 pinctrl-names = "default"; 742 status = "disabled"; 743 }; 744 745 cru: clock-controller@ff500000 { 746 compatible = "rockchip,rk3308-cru"; 747 reg = <0x0 0xff500000 0x0 0x1000>; 748 #clock-cells = <1>; 749 #reset-cells = <1>; 750 rockchip,grf = <&grf>; 751 752 assigned-clocks = <&cru SCLK_RTC32K>; 753 assigned-clock-rates = <32768>; 754 }; 755 756 gic: interrupt-controller@ff580000 { 757 compatible = "arm,gic-400"; 758 reg = <0x0 0xff581000 0x0 0x1000>, 759 <0x0 0xff582000 0x0 0x2000>, 760 <0x0 0xff584000 0x0 0x2000>, 761 <0x0 0xff586000 0x0 0x2000>; 762 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 763 #interrupt-cells = <3>; 764 interrupt-controller; 765 #address-cells = <0>; 766 }; 767 768 sram: sram@fff80000 { 769 compatible = "mmio-sram"; 770 reg = <0x0 0xfff80000 0x0 0x40000>; 771 ranges = <0 0x0 0xfff80000 0x40000>; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 775 /* reserved for ddr dvfs and system suspend/resume */ 776 ddr-sram@0 { 777 reg = <0x0 0x8000>; 778 }; 779 780 /* reserved for vad audio buffer */ 781 vad_sram: vad-sram@8000 { 782 reg = <0x8000 0x38000>; 783 }; 784 }; 785 786 pinctrl: pinctrl { 787 compatible = "rockchip,rk3308-pinctrl"; 788 rockchip,grf = <&grf>; 789 #address-cells = <2>; 790 #size-cells = <2>; 791 ranges; 792 793 gpio0: gpio@ff220000 { 794 compatible = "rockchip,gpio-bank"; 795 reg = <0x0 0xff220000 0x0 0x100>; 796 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cru PCLK_GPIO0>; 798 gpio-controller; 799 #gpio-cells = <2>; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 }; 803 804 gpio1: gpio@ff230000 { 805 compatible = "rockchip,gpio-bank"; 806 reg = <0x0 0xff230000 0x0 0x100>; 807 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&cru PCLK_GPIO1>; 809 gpio-controller; 810 #gpio-cells = <2>; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 }; 814 815 gpio2: gpio@ff240000 { 816 compatible = "rockchip,gpio-bank"; 817 reg = <0x0 0xff240000 0x0 0x100>; 818 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&cru PCLK_GPIO2>; 820 gpio-controller; 821 #gpio-cells = <2>; 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 }; 825 826 gpio3: gpio@ff250000 { 827 compatible = "rockchip,gpio-bank"; 828 reg = <0x0 0xff250000 0x0 0x100>; 829 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cru PCLK_GPIO3>; 831 gpio-controller; 832 #gpio-cells = <2>; 833 interrupt-controller; 834 #interrupt-cells = <2>; 835 }; 836 837 gpio4: gpio@ff260000 { 838 compatible = "rockchip,gpio-bank"; 839 reg = <0x0 0xff260000 0x0 0x100>; 840 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cru PCLK_GPIO4>; 842 gpio-controller; 843 #gpio-cells = <2>; 844 interrupt-controller; 845 #interrupt-cells = <2>; 846 }; 847 848 pcfg_pull_up: pcfg-pull-up { 849 bias-pull-up; 850 }; 851 852 pcfg_pull_down: pcfg-pull-down { 853 bias-pull-down; 854 }; 855 856 pcfg_pull_none: pcfg-pull-none { 857 bias-disable; 858 }; 859 860 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 861 bias-disable; 862 drive-strength = <2>; 863 }; 864 865 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 866 bias-pull-up; 867 drive-strength = <2>; 868 }; 869 870 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 871 bias-pull-up; 872 drive-strength = <4>; 873 }; 874 875 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 876 bias-disable; 877 drive-strength = <4>; 878 }; 879 880 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 881 bias-pull-down; 882 drive-strength = <4>; 883 }; 884 885 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 886 bias-disable; 887 drive-strength = <8>; 888 }; 889 890 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 891 bias-pull-up; 892 drive-strength = <8>; 893 }; 894 895 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 896 bias-disable; 897 drive-strength = <12>; 898 }; 899 900 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 901 bias-pull-up; 902 drive-strength = <12>; 903 }; 904 905 pcfg_pull_none_smt: pcfg-pull-none-smt { 906 bias-disable; 907 input-schmitt-enable; 908 }; 909 910 pcfg_output_high: pcfg-output-high { 911 output-high; 912 }; 913 914 pcfg_output_low: pcfg-output-low { 915 output-low; 916 }; 917 918 pcfg_input_high: pcfg-input-high { 919 bias-pull-up; 920 input-enable; 921 }; 922 923 pcfg_input: pcfg-input { 924 input-enable; 925 }; 926 927 emmc { 928 emmc_clk: emmc-clk { 929 rockchip,pins = 930 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 931 }; 932 933 emmc_cmd: emmc-cmd { 934 rockchip,pins = 935 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 936 }; 937 938 emmc_pwren: emmc-pwren { 939 rockchip,pins = 940 <3 RK_PB3 2 &pcfg_pull_none>; 941 }; 942 943 emmc_rstn: emmc-rstn { 944 rockchip,pins = 945 <3 RK_PB2 2 &pcfg_pull_none>; 946 }; 947 948 emmc_bus1: emmc-bus1 { 949 rockchip,pins = 950 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 951 }; 952 953 emmc_bus4: emmc-bus4 { 954 rockchip,pins = 955 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 956 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 957 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 958 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 959 }; 960 961 emmc_bus8: emmc-bus8 { 962 rockchip,pins = 963 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 964 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 965 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 966 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 967 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 968 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 969 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 970 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 971 }; 972 }; 973 974 flash { 975 flash_csn0: flash-csn0 { 976 rockchip,pins = 977 <3 RK_PB5 1 &pcfg_pull_none>; 978 }; 979 980 flash_rdy: flash-rdy { 981 rockchip,pins = 982 <3 RK_PB4 1 &pcfg_pull_none>; 983 }; 984 985 flash_ale: flash-ale { 986 rockchip,pins = 987 <3 RK_PB3 1 &pcfg_pull_none>; 988 }; 989 990 flash_cle: flash-cle { 991 rockchip,pins = 992 <3 RK_PB1 1 &pcfg_pull_none>; 993 }; 994 995 flash_wrn: flash-wrn { 996 rockchip,pins = 997 <3 RK_PB0 1 &pcfg_pull_none>; 998 }; 999 1000 flash_rdn: flash-rdn { 1001 rockchip,pins = 1002 <3 RK_PB2 1 &pcfg_pull_none>; 1003 }; 1004 1005 flash_bus8: flash-bus8 { 1006 rockchip,pins = 1007 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1008 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1009 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1010 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1011 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1012 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1013 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1014 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1015 }; 1016 }; 1017 1018 sfc { 1019 sfc_bus4: sfc-bus4 { 1020 rockchip,pins = 1021 <3 RK_PA0 3 &pcfg_pull_none>, 1022 <3 RK_PA1 3 &pcfg_pull_none>, 1023 <3 RK_PA2 3 &pcfg_pull_none>, 1024 <3 RK_PA3 3 &pcfg_pull_none>; 1025 }; 1026 1027 sfc_bus2: sfc-bus2 { 1028 rockchip,pins = 1029 <3 RK_PA0 3 &pcfg_pull_none>, 1030 <3 RK_PA1 3 &pcfg_pull_none>; 1031 }; 1032 1033 sfc_cs0: sfc-cs0 { 1034 rockchip,pins = 1035 <3 RK_PA4 3 &pcfg_pull_none>; 1036 }; 1037 1038 sfc_clk: sfc-clk { 1039 rockchip,pins = 1040 <3 RK_PA5 3 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 gmac { 1045 rmii_pins: rmii-pins { 1046 rockchip,pins = 1047 /* mac_txen */ 1048 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1049 /* mac_txd1 */ 1050 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1051 /* mac_txd0 */ 1052 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1053 /* mac_rxd0 */ 1054 <1 RK_PC4 3 &pcfg_pull_none>, 1055 /* mac_rxd1 */ 1056 <1 RK_PC5 3 &pcfg_pull_none>, 1057 /* mac_rxer */ 1058 <1 RK_PB7 3 &pcfg_pull_none>, 1059 /* mac_rxdv */ 1060 <1 RK_PC0 3 &pcfg_pull_none>, 1061 /* mac_mdio */ 1062 <1 RK_PB6 3 &pcfg_pull_none>, 1063 /* mac_mdc */ 1064 <1 RK_PB5 3 &pcfg_pull_none>; 1065 }; 1066 1067 mac_refclk_12ma: mac-refclk-12ma { 1068 rockchip,pins = 1069 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1070 }; 1071 1072 mac_refclk: mac-refclk { 1073 rockchip,pins = 1074 <1 RK_PB4 3 &pcfg_pull_none>; 1075 }; 1076 }; 1077 1078 gmac-m1 { 1079 rmiim1_pins: rmiim1-pins { 1080 rockchip,pins = 1081 /* mac_txen */ 1082 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 1083 /* mac_txd1 */ 1084 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 1085 /* mac_txd0 */ 1086 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 1087 /* mac_rxd0 */ 1088 <4 RK_PA2 2 &pcfg_pull_none>, 1089 /* mac_rxd1 */ 1090 <4 RK_PA3 2 &pcfg_pull_none>, 1091 /* mac_rxer */ 1092 <4 RK_PA0 2 &pcfg_pull_none>, 1093 /* mac_rxdv */ 1094 <4 RK_PA1 2 &pcfg_pull_none>, 1095 /* mac_mdio */ 1096 <4 RK_PB6 2 &pcfg_pull_none>, 1097 /* mac_mdc */ 1098 <4 RK_PB5 2 &pcfg_pull_none>; 1099 }; 1100 1101 macm1_refclk_12ma: macm1-refclk-12ma { 1102 rockchip,pins = 1103 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 1104 }; 1105 1106 macm1_refclk: macm1-refclk { 1107 rockchip,pins = 1108 <4 RK_PB4 2 &pcfg_pull_none>; 1109 }; 1110 }; 1111 1112 i2c0 { 1113 i2c0_xfer: i2c0-xfer { 1114 rockchip,pins = 1115 <1 RK_PD0 2 &pcfg_pull_none_smt>, 1116 <1 RK_PD1 2 &pcfg_pull_none_smt>; 1117 }; 1118 }; 1119 1120 i2c1 { 1121 i2c1_xfer: i2c1-xfer { 1122 rockchip,pins = 1123 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1124 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1125 }; 1126 }; 1127 1128 i2c2 { 1129 i2c2_xfer: i2c2-xfer { 1130 rockchip,pins = 1131 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1132 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1133 }; 1134 }; 1135 1136 i2c3-m0 { 1137 i2c3m0_xfer: i2c3m0-xfer { 1138 rockchip,pins = 1139 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1140 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1141 }; 1142 }; 1143 1144 i2c3-m1 { 1145 i2c3m1_xfer: i2c3m1-xfer { 1146 rockchip,pins = 1147 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1148 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1149 }; 1150 }; 1151 1152 i2c3-m2 { 1153 i2c3m2_xfer: i2c3m2-xfer { 1154 rockchip,pins = 1155 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1156 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1157 }; 1158 }; 1159 1160 i2s_2ch_0 { 1161 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1162 rockchip,pins = 1163 <4 RK_PB4 1 &pcfg_pull_none>; 1164 }; 1165 1166 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1167 rockchip,pins = 1168 <4 RK_PB5 1 &pcfg_pull_none>; 1169 }; 1170 1171 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1172 rockchip,pins = 1173 <4 RK_PB6 1 &pcfg_pull_none>; 1174 }; 1175 1176 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1177 rockchip,pins = 1178 <4 RK_PB7 1 &pcfg_pull_none>; 1179 }; 1180 1181 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1182 rockchip,pins = 1183 <4 RK_PC0 1 &pcfg_pull_none>; 1184 }; 1185 }; 1186 1187 i2s_8ch_0 { 1188 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1189 rockchip,pins = 1190 <2 RK_PA4 1 &pcfg_pull_none>; 1191 }; 1192 1193 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1194 rockchip,pins = 1195 <2 RK_PA5 1 &pcfg_pull_none>; 1196 }; 1197 1198 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1199 rockchip,pins = 1200 <2 RK_PA6 1 &pcfg_pull_none>; 1201 }; 1202 1203 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1204 rockchip,pins = 1205 <2 RK_PA7 1 &pcfg_pull_none>; 1206 }; 1207 1208 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1209 rockchip,pins = 1210 <2 RK_PB0 1 &pcfg_pull_none>; 1211 }; 1212 1213 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1214 rockchip,pins = 1215 <2 RK_PB1 1 &pcfg_pull_none>; 1216 }; 1217 1218 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1219 rockchip,pins = 1220 <2 RK_PB2 1 &pcfg_pull_none>; 1221 }; 1222 1223 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1224 rockchip,pins = 1225 <2 RK_PB3 1 &pcfg_pull_none>; 1226 }; 1227 1228 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1229 rockchip,pins = 1230 <2 RK_PB4 1 &pcfg_pull_none>; 1231 }; 1232 1233 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1234 rockchip,pins = 1235 <2 RK_PB5 1 &pcfg_pull_none>; 1236 }; 1237 1238 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1239 rockchip,pins = 1240 <2 RK_PB6 1 &pcfg_pull_none>; 1241 }; 1242 1243 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1244 rockchip,pins = 1245 <2 RK_PB7 1 &pcfg_pull_none>; 1246 }; 1247 1248 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1249 rockchip,pins = 1250 <2 RK_PC0 1 &pcfg_pull_none>; 1251 }; 1252 }; 1253 1254 i2s_8ch_1_m0 { 1255 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1256 rockchip,pins = 1257 <1 RK_PA2 2 &pcfg_pull_none>; 1258 }; 1259 1260 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1261 rockchip,pins = 1262 <1 RK_PA3 2 &pcfg_pull_none>; 1263 }; 1264 1265 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1266 rockchip,pins = 1267 <1 RK_PA4 2 &pcfg_pull_none>; 1268 }; 1269 1270 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1271 rockchip,pins = 1272 <1 RK_PA5 2 &pcfg_pull_none>; 1273 }; 1274 1275 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1276 rockchip,pins = 1277 <1 RK_PA6 2 &pcfg_pull_none>; 1278 }; 1279 1280 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1281 rockchip,pins = 1282 <1 RK_PA7 2 &pcfg_pull_none>; 1283 }; 1284 1285 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1286 rockchip,pins = 1287 <1 RK_PB0 2 &pcfg_pull_none>; 1288 }; 1289 1290 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1291 rockchip,pins = 1292 <1 RK_PB1 2 &pcfg_pull_none>; 1293 }; 1294 1295 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1296 rockchip,pins = 1297 <1 RK_PB2 2 &pcfg_pull_none>; 1298 }; 1299 1300 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1301 rockchip,pins = 1302 <1 RK_PB3 2 &pcfg_pull_none>; 1303 }; 1304 }; 1305 1306 i2s_8ch_1_m1 { 1307 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1308 rockchip,pins = 1309 <1 RK_PB4 2 &pcfg_pull_none>; 1310 }; 1311 1312 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1313 rockchip,pins = 1314 <1 RK_PB5 2 &pcfg_pull_none>; 1315 }; 1316 1317 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1318 rockchip,pins = 1319 <1 RK_PB6 2 &pcfg_pull_none>; 1320 }; 1321 1322 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1323 rockchip,pins = 1324 <1 RK_PB7 2 &pcfg_pull_none>; 1325 }; 1326 1327 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1328 rockchip,pins = 1329 <1 RK_PC0 2 &pcfg_pull_none>; 1330 }; 1331 1332 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1333 rockchip,pins = 1334 <1 RK_PC1 2 &pcfg_pull_none>; 1335 }; 1336 1337 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1338 rockchip,pins = 1339 <1 RK_PC2 2 &pcfg_pull_none>; 1340 }; 1341 1342 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1343 rockchip,pins = 1344 <1 RK_PC3 2 &pcfg_pull_none>; 1345 }; 1346 1347 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1348 rockchip,pins = 1349 <1 RK_PC4 2 &pcfg_pull_none>; 1350 }; 1351 1352 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1353 rockchip,pins = 1354 <1 RK_PC5 2 &pcfg_pull_none>; 1355 }; 1356 }; 1357 1358 pdm_m0 { 1359 pdm_m0_clk: pdm-m0-clk { 1360 rockchip,pins = 1361 <1 RK_PA4 3 &pcfg_pull_none>; 1362 }; 1363 1364 pdm_m0_sdi0: pdm-m0-sdi0 { 1365 rockchip,pins = 1366 <1 RK_PB3 3 &pcfg_pull_none>; 1367 }; 1368 1369 pdm_m0_sdi1: pdm-m0-sdi1 { 1370 rockchip,pins = 1371 <1 RK_PB2 3 &pcfg_pull_none>; 1372 }; 1373 1374 pdm_m0_sdi2: pdm-m0-sdi2 { 1375 rockchip,pins = 1376 <1 RK_PB1 3 &pcfg_pull_none>; 1377 }; 1378 1379 pdm_m0_sdi3: pdm-m0-sdi3 { 1380 rockchip,pins = 1381 <1 RK_PB0 3 &pcfg_pull_none>; 1382 }; 1383 }; 1384 1385 pdm_m1 { 1386 pdm_m1_clk: pdm-m1-clk { 1387 rockchip,pins = 1388 <1 RK_PB6 4 &pcfg_pull_none>; 1389 }; 1390 1391 pdm_m1_sdi0: pdm-m1-sdi0 { 1392 rockchip,pins = 1393 <1 RK_PC5 4 &pcfg_pull_none>; 1394 }; 1395 1396 pdm_m1_sdi1: pdm-m1-sdi1 { 1397 rockchip,pins = 1398 <1 RK_PC4 4 &pcfg_pull_none>; 1399 }; 1400 1401 pdm_m1_sdi2: pdm-m1-sdi2 { 1402 rockchip,pins = 1403 <1 RK_PC3 4 &pcfg_pull_none>; 1404 }; 1405 1406 pdm_m1_sdi3: pdm-m1-sdi3 { 1407 rockchip,pins = 1408 <1 RK_PC2 4 &pcfg_pull_none>; 1409 }; 1410 }; 1411 1412 pdm_m2 { 1413 pdm_m2_clkm: pdm-m2-clkm { 1414 rockchip,pins = 1415 <2 RK_PA4 3 &pcfg_pull_none>; 1416 }; 1417 1418 pdm_m2_clk: pdm-m2-clk { 1419 rockchip,pins = 1420 <2 RK_PA6 2 &pcfg_pull_none>; 1421 }; 1422 1423 pdm_m2_sdi0: pdm-m2-sdi0 { 1424 rockchip,pins = 1425 <2 RK_PB5 2 &pcfg_pull_none>; 1426 }; 1427 1428 pdm_m2_sdi1: pdm-m2-sdi1 { 1429 rockchip,pins = 1430 <2 RK_PB6 2 &pcfg_pull_none>; 1431 }; 1432 1433 pdm_m2_sdi2: pdm-m2-sdi2 { 1434 rockchip,pins = 1435 <2 RK_PB7 2 &pcfg_pull_none>; 1436 }; 1437 1438 pdm_m2_sdi3: pdm-m2-sdi3 { 1439 rockchip,pins = 1440 <2 RK_PC0 2 &pcfg_pull_none>; 1441 }; 1442 }; 1443 1444 pwm0 { 1445 pwm0_pin: pwm0-pin { 1446 rockchip,pins = 1447 <0 RK_PB5 1 &pcfg_pull_none>; 1448 }; 1449 1450 pwm0_pin_pull_down: pwm0-pin-pull-down { 1451 rockchip,pins = 1452 <0 RK_PB5 1 &pcfg_pull_down>; 1453 }; 1454 }; 1455 1456 pwm1 { 1457 pwm1_pin: pwm1-pin { 1458 rockchip,pins = 1459 <0 RK_PB6 1 &pcfg_pull_none>; 1460 }; 1461 1462 pwm1_pin_pull_down: pwm1-pin-pull-down { 1463 rockchip,pins = 1464 <0 RK_PB6 1 &pcfg_pull_down>; 1465 }; 1466 }; 1467 1468 pwm2 { 1469 pwm2_pin: pwm2-pin { 1470 rockchip,pins = 1471 <0 RK_PB7 1 &pcfg_pull_none>; 1472 }; 1473 1474 pwm2_pin_pull_down: pwm2-pin-pull-down { 1475 rockchip,pins = 1476 <0 RK_PB7 1 &pcfg_pull_down>; 1477 }; 1478 }; 1479 1480 pwm3 { 1481 pwm3_pin: pwm3-pin { 1482 rockchip,pins = 1483 <0 RK_PC0 1 &pcfg_pull_none>; 1484 }; 1485 1486 pwm3_pin_pull_down: pwm3-pin-pull-down { 1487 rockchip,pins = 1488 <0 RK_PC0 1 &pcfg_pull_down>; 1489 }; 1490 }; 1491 1492 pwm4 { 1493 pwm4_pin: pwm4-pin { 1494 rockchip,pins = 1495 <0 RK_PA1 2 &pcfg_pull_none>; 1496 }; 1497 1498 pwm4_pin_pull_down: pwm4-pin-pull-down { 1499 rockchip,pins = 1500 <0 RK_PA1 2 &pcfg_pull_down>; 1501 }; 1502 }; 1503 1504 pwm5 { 1505 pwm5_pin: pwm5-pin { 1506 rockchip,pins = 1507 <0 RK_PC1 2 &pcfg_pull_none>; 1508 }; 1509 1510 pwm5_pin_pull_down: pwm5-pin-pull-down { 1511 rockchip,pins = 1512 <0 RK_PC1 2 &pcfg_pull_down>; 1513 }; 1514 }; 1515 1516 pwm6 { 1517 pwm6_pin: pwm6-pin { 1518 rockchip,pins = 1519 <0 RK_PC2 2 &pcfg_pull_none>; 1520 }; 1521 1522 pwm6_pin_pull_down: pwm6-pin-pull-down { 1523 rockchip,pins = 1524 <0 RK_PC2 2 &pcfg_pull_down>; 1525 }; 1526 }; 1527 1528 pwm7 { 1529 pwm7_pin: pwm7-pin { 1530 rockchip,pins = 1531 <2 RK_PB0 2 &pcfg_pull_none>; 1532 }; 1533 1534 pwm7_pin_pull_down: pwm7-pin-pull-down { 1535 rockchip,pins = 1536 <2 RK_PB0 2 &pcfg_pull_down>; 1537 }; 1538 }; 1539 1540 pwm8 { 1541 pwm8_pin: pwm8-pin { 1542 rockchip,pins = 1543 <2 RK_PB2 2 &pcfg_pull_none>; 1544 }; 1545 1546 pwm8_pin_pull_down: pwm8-pin-pull-down { 1547 rockchip,pins = 1548 <2 RK_PB2 2 &pcfg_pull_down>; 1549 }; 1550 }; 1551 1552 pwm9 { 1553 pwm9_pin: pwm9-pin { 1554 rockchip,pins = 1555 <2 RK_PB3 2 &pcfg_pull_none>; 1556 }; 1557 1558 pwm9_pin_pull_down: pwm9-pin-pull-down { 1559 rockchip,pins = 1560 <2 RK_PB3 2 &pcfg_pull_down>; 1561 }; 1562 }; 1563 1564 pwm10 { 1565 pwm10_pin: pwm10-pin { 1566 rockchip,pins = 1567 <2 RK_PB4 2 &pcfg_pull_none>; 1568 }; 1569 1570 pwm10_pin_pull_down: pwm10-pin-pull-down { 1571 rockchip,pins = 1572 <2 RK_PB4 2 &pcfg_pull_down>; 1573 }; 1574 }; 1575 1576 pwm11 { 1577 pwm11_pin: pwm11-pin { 1578 rockchip,pins = 1579 <2 RK_PC0 4 &pcfg_pull_none>; 1580 }; 1581 1582 pwm11_pin_pull_down: pwm11-pin-pull-down { 1583 rockchip,pins = 1584 <2 RK_PC0 4 &pcfg_pull_down>; 1585 }; 1586 }; 1587 1588 rtc { 1589 rtc_32k: rtc-32k { 1590 rockchip,pins = 1591 <0 RK_PC3 1 &pcfg_pull_none>; 1592 }; 1593 }; 1594 1595 sdmmc { 1596 sdmmc_clk: sdmmc-clk { 1597 rockchip,pins = 1598 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1599 }; 1600 1601 sdmmc_cmd: sdmmc-cmd { 1602 rockchip,pins = 1603 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1604 }; 1605 1606 sdmmc_det: sdmmc-det { 1607 rockchip,pins = 1608 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1609 }; 1610 1611 sdmmc_pwren: sdmmc-pwren { 1612 rockchip,pins = 1613 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1614 }; 1615 1616 sdmmc_bus1: sdmmc-bus1 { 1617 rockchip,pins = 1618 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1619 }; 1620 1621 sdmmc_bus4: sdmmc-bus4 { 1622 rockchip,pins = 1623 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1624 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1625 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1626 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1627 }; 1628 }; 1629 1630 sdio { 1631 sdio_clk: sdio-clk { 1632 rockchip,pins = 1633 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1634 }; 1635 1636 sdio_cmd: sdio-cmd { 1637 rockchip,pins = 1638 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1639 }; 1640 1641 sdio_pwren: sdio-pwren { 1642 rockchip,pins = 1643 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1644 }; 1645 1646 sdio_wrpt: sdio-wrpt { 1647 rockchip,pins = 1648 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1649 }; 1650 1651 sdio_intn: sdio-intn { 1652 rockchip,pins = 1653 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1654 }; 1655 1656 sdio_bus1: sdio-bus1 { 1657 rockchip,pins = 1658 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1659 }; 1660 1661 sdio_bus4: sdio-bus4 { 1662 rockchip,pins = 1663 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1664 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1665 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1666 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1667 }; 1668 }; 1669 1670 spdif_in { 1671 spdif_in: spdif-in { 1672 rockchip,pins = 1673 <0 RK_PC2 1 &pcfg_pull_none>; 1674 }; 1675 }; 1676 1677 spdif_out { 1678 spdif_out: spdif-out { 1679 rockchip,pins = 1680 <0 RK_PC1 1 &pcfg_pull_none>; 1681 }; 1682 }; 1683 1684 spi0 { 1685 spi0_clk: spi0-clk { 1686 rockchip,pins = 1687 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1688 }; 1689 1690 spi0_csn0: spi0-csn0 { 1691 rockchip,pins = 1692 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1693 }; 1694 1695 spi0_miso: spi0-miso { 1696 rockchip,pins = 1697 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1698 }; 1699 1700 spi0_mosi: spi0-mosi { 1701 rockchip,pins = 1702 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1703 }; 1704 }; 1705 1706 spi1 { 1707 spi1_clk: spi1-clk { 1708 rockchip,pins = 1709 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1710 }; 1711 1712 spi1_csn0: spi1-csn0 { 1713 rockchip,pins = 1714 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1715 }; 1716 1717 spi1_miso: spi1-miso { 1718 rockchip,pins = 1719 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1720 }; 1721 1722 spi1_mosi: spi1-mosi { 1723 rockchip,pins = 1724 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1725 }; 1726 }; 1727 1728 spi1-m1 { 1729 spi1m1_miso: spi1m1-miso { 1730 rockchip,pins = 1731 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1732 }; 1733 1734 spi1m1_mosi: spi1m1-mosi { 1735 rockchip,pins = 1736 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1737 }; 1738 1739 spi1m1_clk: spi1m1-clk { 1740 rockchip,pins = 1741 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1742 }; 1743 1744 spi1m1_csn0: spi1m1-csn0 { 1745 rockchip,pins = 1746 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1747 }; 1748 }; 1749 1750 spi2 { 1751 spi2_clk: spi2-clk { 1752 rockchip,pins = 1753 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1754 }; 1755 1756 spi2_csn0: spi2-csn0 { 1757 rockchip,pins = 1758 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1759 }; 1760 1761 spi2_miso: spi2-miso { 1762 rockchip,pins = 1763 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1764 }; 1765 1766 spi2_mosi: spi2-mosi { 1767 rockchip,pins = 1768 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1769 }; 1770 }; 1771 1772 tsadc { 1773 tsadc_otp_pin: tsadc-otp-pin { 1774 rockchip,pins = 1775 <0 RK_PB2 0 &pcfg_pull_none>; 1776 }; 1777 1778 tsadc_otp_out: tsadc-otp-out { 1779 rockchip,pins = 1780 <0 RK_PB2 1 &pcfg_pull_none>; 1781 }; 1782 }; 1783 1784 uart0 { 1785 uart0_xfer: uart0-xfer { 1786 rockchip,pins = 1787 <2 RK_PA1 1 &pcfg_pull_up>, 1788 <2 RK_PA0 1 &pcfg_pull_up>; 1789 }; 1790 1791 uart0_cts: uart0-cts { 1792 rockchip,pins = 1793 <2 RK_PA2 1 &pcfg_pull_none>; 1794 }; 1795 1796 uart0_rts: uart0-rts { 1797 rockchip,pins = 1798 <2 RK_PA3 1 &pcfg_pull_none>; 1799 }; 1800 1801 uart0_rts_pin: uart0-rts-pin { 1802 rockchip,pins = 1803 <2 RK_PA3 0 &pcfg_pull_none>; 1804 }; 1805 }; 1806 1807 uart1 { 1808 uart1_xfer: uart1-xfer { 1809 rockchip,pins = 1810 <1 RK_PD1 1 &pcfg_pull_up>, 1811 <1 RK_PD0 1 &pcfg_pull_up>; 1812 }; 1813 1814 uart1_cts: uart1-cts { 1815 rockchip,pins = 1816 <1 RK_PC6 1 &pcfg_pull_none>; 1817 }; 1818 1819 uart1_rts: uart1-rts { 1820 rockchip,pins = 1821 <1 RK_PC7 1 &pcfg_pull_none>; 1822 }; 1823 }; 1824 1825 uart2-m0 { 1826 uart2m0_xfer: uart2m0-xfer { 1827 rockchip,pins = 1828 <1 RK_PC7 2 &pcfg_pull_up>, 1829 <1 RK_PC6 2 &pcfg_pull_up>; 1830 }; 1831 }; 1832 1833 uart2-m1 { 1834 uart2m1_xfer: uart2m1-xfer { 1835 rockchip,pins = 1836 <4 RK_PD3 2 &pcfg_pull_up>, 1837 <4 RK_PD2 2 &pcfg_pull_up>; 1838 }; 1839 }; 1840 1841 uart3 { 1842 uart3_xfer: uart3-xfer { 1843 rockchip,pins = 1844 <3 RK_PB5 4 &pcfg_pull_up>, 1845 <3 RK_PB4 4 &pcfg_pull_up>; 1846 }; 1847 }; 1848 1849 uart3-m1 { 1850 uart3m1_xfer: uart3m1-xfer { 1851 rockchip,pins = 1852 <0 RK_PC2 3 &pcfg_pull_up>, 1853 <0 RK_PC1 3 &pcfg_pull_up>; 1854 }; 1855 }; 1856 1857 uart4 { 1858 uart4_xfer: uart4-xfer { 1859 rockchip,pins = 1860 <4 RK_PB1 1 &pcfg_pull_up>, 1861 <4 RK_PB0 1 &pcfg_pull_up>; 1862 }; 1863 1864 uart4_cts: uart4-cts { 1865 rockchip,pins = 1866 <4 RK_PA6 1 &pcfg_pull_none>; 1867 }; 1868 1869 uart4_rts: uart4-rts { 1870 rockchip,pins = 1871 <4 RK_PA7 1 &pcfg_pull_none>; 1872 }; 1873 1874 uart4_rts_pin: uart4-rts-pin { 1875 rockchip,pins = 1876 <4 RK_PA7 0 &pcfg_pull_none>; 1877 }; 1878 }; 1879 }; 1880}; 1881