1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH 4 */ 5 6/dts-v1/; 7#include "px30.dtsi" 8#include <dt-bindings/leds/common.h> 9 10/ { 11 aliases { 12 i2c10 = &i2c10; 13 mmc0 = &emmc; 14 mmc1 = &sdio; 15 rtc0 = &rtc_twi; 16 rtc1 = &rk809; 17 }; 18 19 /* allows userspace to control the gate of the ATtiny UPDI pass FET via sysfs */ 20 attiny-updi-gate-regulator { 21 compatible = "regulator-output"; 22 vout-supply = <&vg_attiny_updi>; 23 }; 24 25 emmc_pwrseq: emmc-pwrseq { 26 compatible = "mmc-pwrseq-emmc"; 27 pinctrl-0 = <&emmc_reset>; 28 pinctrl-names = "default"; 29 reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; 30 }; 31 32 leds { 33 compatible = "gpio-leds"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&module_led_pin>; 36 status = "okay"; 37 38 module_led: led-0 { 39 gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 40 function = LED_FUNCTION_HEARTBEAT; 41 linux,default-trigger = "heartbeat"; 42 color = <LED_COLOR_ID_AMBER>; 43 }; 44 }; 45 46 vcc5v0_sys: regulator-vccsys { 47 compatible = "regulator-fixed"; 48 regulator-name = "vcc5v0_sys"; 49 regulator-always-on; 50 regulator-boot-on; 51 regulator-min-microvolt = <5000000>; 52 regulator-max-microvolt = <5000000>; 53 }; 54}; 55 56&cpu0 { 57 cpu-supply = <&vdd_arm>; 58}; 59 60&cpu1 { 61 cpu-supply = <&vdd_arm>; 62}; 63 64&cpu2 { 65 cpu-supply = <&vdd_arm>; 66}; 67 68&cpu3 { 69 cpu-supply = <&vdd_arm>; 70}; 71 72&emmc { 73 bus-width = <8>; 74 cap-mmc-highspeed; 75 mmc-hs200-1_8v; 76 mmc-pwrseq = <&emmc_pwrseq>; 77 non-removable; 78 vmmc-supply = <&vcc_3v3>; 79 vqmmc-supply = <&vcc_emmc>; 80 81 status = "okay"; 82}; 83 84/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ 85&gmac { 86 phy-handle = <&dp83825>; 87 phy-supply = <&vcc_3v3>; 88 clock_in_out = "output"; 89}; 90 91&gpio2 { 92 /* 93 * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module 94 * eMMC powered-down initially (in fact it keeps the reset signal 95 * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after 96 * the SPL has been booted from SD Card. 97 */ 98 bios-disable-override-hog { 99 gpios = <RK_PB5 GPIO_ACTIVE_LOW>; 100 output-high; 101 line-name = "bios_disable_override"; 102 gpio-hog; 103 }; 104 105 /* 106 * The BIOS_DISABLE hog is a feedback pin for the actual status of the 107 * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually 108 * represents the state of a switch on the baseboard. 109 */ 110 bios-disable-n-hog { 111 gpios = <RK_PC2 GPIO_ACTIVE_LOW>; 112 line-name = "bios_disable"; 113 input; 114 gpio-hog; 115 }; 116}; 117 118&gpu { 119 status = "okay"; 120}; 121 122&i2c0 { 123 status = "okay"; 124 125 rk809: pmic@20 { 126 compatible = "rockchip,rk809"; 127 reg = <0x20>; 128 interrupt-parent = <&gpio0>; 129 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 130 pinctrl-0 = <&pmic_int>; 131 pinctrl-names = "default"; 132 #clock-cells = <0>; 133 clock-output-names = "xin32k"; 134 system-power-controller; 135 wakeup-source; 136 137 vcc1-supply = <&vcc5v0_sys>; 138 vcc2-supply = <&vcc5v0_sys>; 139 vcc3-supply = <&vcc5v0_sys>; 140 vcc4-supply = <&vcc5v0_sys>; 141 vcc5-supply = <&vcc_3v3>; 142 vcc6-supply = <&vcc_3v3>; 143 vcc7-supply = <&vcc_3v3>; 144 vcc9-supply = <&vcc5v0_sys>; 145 146 regulators { 147 vdd_log: DCDC_REG1 { 148 regulator-name = "vdd_log"; 149 regulator-min-microvolt = <950000>; 150 regulator-max-microvolt = <1350000>; 151 regulator-ramp-delay = <6001>; 152 regulator-always-on; 153 regulator-boot-on; 154 155 regulator-state-mem { 156 regulator-on-in-suspend; 157 regulator-suspend-microvolt = <950000>; 158 }; 159 }; 160 161 vdd_arm: DCDC_REG2 { 162 regulator-name = "vdd_arm"; 163 regulator-min-microvolt = <950000>; 164 regulator-max-microvolt = <1350000>; 165 regulator-ramp-delay = <6001>; 166 regulator-always-on; 167 regulator-boot-on; 168 169 regulator-state-mem { 170 regulator-off-in-suspend; 171 regulator-suspend-microvolt = <950000>; 172 }; 173 }; 174 175 vcc_ddr: DCDC_REG3 { 176 regulator-name = "vcc_ddr"; 177 regulator-always-on; 178 regulator-boot-on; 179 180 regulator-state-mem { 181 regulator-on-in-suspend; 182 }; 183 }; 184 185 vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { 186 regulator-name = "vcc_3v0_1v8"; 187 regulator-min-microvolt = <1800000>; 188 regulator-max-microvolt = <3000000>; 189 regulator-always-on; 190 regulator-boot-on; 191 192 regulator-state-mem { 193 regulator-on-in-suspend; 194 regulator-suspend-microvolt = <3000000>; 195 }; 196 }; 197 198 vcc_3v3: DCDC_REG5 { 199 regulator-name = "vcc_3v3"; 200 regulator-min-microvolt = <3300000>; 201 regulator-max-microvolt = <3300000>; 202 regulator-always-on; 203 regulator-boot-on; 204 205 regulator-state-mem { 206 regulator-on-in-suspend; 207 regulator-suspend-microvolt = <3300000>; 208 }; 209 }; 210 211 vcc_1v8: LDO_REG2 { 212 regulator-name = "vcc_1v8"; 213 regulator-min-microvolt = <1800000>; 214 regulator-max-microvolt = <1800000>; 215 regulator-always-on; 216 regulator-boot-on; 217 218 regulator-state-mem { 219 regulator-on-in-suspend; 220 regulator-suspend-microvolt = <1800000>; 221 }; 222 }; 223 224 vcc_1v0: LDO_REG3 { 225 regulator-name = "vcc_1v0"; 226 regulator-min-microvolt = <1000000>; 227 regulator-max-microvolt = <1000000>; 228 regulator-always-on; 229 regulator-boot-on; 230 231 regulator-state-mem { 232 regulator-on-in-suspend; 233 regulator-suspend-microvolt = <1000000>; 234 }; 235 }; 236 237 vccio_sd: LDO_REG5 { 238 regulator-name = "vccio_sd"; 239 regulator-min-microvolt = <1800000>; 240 regulator-max-microvolt = <3300000>; 241 regulator-always-on; 242 regulator-boot-on; 243 244 regulator-state-mem { 245 regulator-on-in-suspend; 246 regulator-suspend-microvolt = <3300000>; 247 }; 248 }; 249 250 vcc_lcd: LDO_REG7 { 251 regulator-always-on; 252 regulator-boot-on; 253 regulator-min-microvolt = <1000000>; 254 regulator-max-microvolt = <1000000>; 255 regulator-name = "vcc_lcd"; 256 257 regulator-state-mem { 258 regulator-off-in-suspend; 259 regulator-suspend-microvolt = <1000000>; 260 }; 261 }; 262 263 vcc_1v8_lcd: LDO_REG8 { 264 regulator-name = "vcc_1v8_lcd"; 265 regulator-min-microvolt = <1800000>; 266 regulator-max-microvolt = <1800000>; 267 regulator-always-on; 268 regulator-boot-on; 269 270 regulator-state-mem { 271 regulator-on-in-suspend; 272 regulator-suspend-microvolt = <1800000>; 273 }; 274 }; 275 276 vcca_1v8: LDO_REG9 { 277 regulator-name = "vcca_1v8"; 278 regulator-min-microvolt = <1800000>; 279 regulator-max-microvolt = <1800000>; 280 regulator-always-on; 281 regulator-boot-on; 282 283 regulator-state-mem { 284 regulator-off-in-suspend; 285 regulator-suspend-microvolt = <1800000>; 286 }; 287 }; 288 289 /* supplies the gate of the ATtiny UPDI pass FET */ 290 vg_attiny_updi: SWITCH_REG1 { 291 regulator-name = "vg_attiny_updi"; 292 }; 293 }; 294 }; 295}; 296 297&i2c1 { 298 status = "okay"; 299 300 /* SE05x is limited to Fast Mode */ 301 clock-frequency = <400000>; 302 303 fan: fan@18 { 304 compatible = "tsd,mule", "ti,amc6821"; 305 reg = <0x18>; 306 307 i2c-mux { 308 compatible = "tsd,mule-i2c-mux"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 i2c10: i2c@0 { 313 reg = <0x0>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 rtc_twi: rtc@6f { 318 compatible = "isil,isl1208"; 319 reg = <0x6f>; 320 }; 321 }; 322 }; 323 }; 324}; 325 326&i2s0_8ch { 327 rockchip,trcm-sync-tx-only; 328 329 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx 330 &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>; 331}; 332 333&io_domains { 334 vccio1-supply = <&vcc_3v3>; 335 vccio2-supply = <&vccio_sd>; 336 vccio3-supply = <&vcc_3v3>; 337 vccio4-supply = <&vcc_3v3>; 338 vccio5-supply = <&vcc_3v3>; 339 vccio6-supply = <&vcc_emmc>; 340 vccio-oscgpi-supply = <&vcc_3v3>; 341 342 status = "okay"; 343}; 344 345&mdio { 346 dp83825: ethernet-phy@0 { 347 compatible = "ethernet-phy-ieee802.3-c22"; 348 reg = <0x0>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&phy_rst>; 351 reset-assert-us = <50000>; 352 reset-deassert-us = <50000>; 353 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 354 }; 355}; 356 357&pinctrl { 358 emmc { 359 emmc_reset: emmc-reset { 360 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 361 }; 362 }; 363 364 ethernet { 365 phy_rst: phy-rst { 366 rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 367 }; 368 }; 369 370 leds { 371 module_led_pin: module-led-pin { 372 rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 373 }; 374 }; 375 376 pmic { 377 pmic_int: pmic-int { 378 rockchip,pins = 379 <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 380 }; 381 }; 382 383 spi1 { 384 spi1_csn0_gpio_pin: spi1-csn0-gpio-pin { 385 rockchip,pins = 386 <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 387 }; 388 389 spi1_csn1_gpio_pin: spi1-csn1-gpio-pin { 390 rockchip,pins = 391 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 392 }; 393 }; 394}; 395 396&pmu_io_domains { 397 pmuio1-supply = <&vcc_3v3>; 398 pmuio2-supply = <&vcc_3v3>; 399 status = "okay"; 400}; 401 402&saradc { 403 vref-supply = <&vcc_1v8>; 404 status = "okay"; 405}; 406 407&sdmmc { 408 vqmmc-supply = <&vccio_sd>; 409}; 410 411&spi1 { 412 /* 413 * Hardware CS has a very slow rise time of about 6us, 414 * causing transmission errors. 415 * With cs-gpios we have a rise time of about 20ns. 416 */ 417 cs-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>, <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&spi1_clk &spi1_csn0_gpio_pin &spi1_csn1_gpio_pin &spi1_miso &spi1_mosi>; 420}; 421 422&tsadc { 423 status = "okay"; 424}; 425 426&u2phy { 427 status = "okay"; 428}; 429 430&u2phy_host { 431 status = "okay"; 432}; 433 434&uart5 { 435 /delete-property/ dmas; 436 /delete-property/ dma-names; 437 pinctrl-0 = <&uart5_xfer>; 438}; 439 440/* Mule UCAN */ 441&usb_host0_ehci { 442 status = "okay"; 443}; 444 445&usb_host0_ohci { 446 status = "okay"; 447}; 448 449&wdt { 450 status = "okay"; 451}; 452