1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 L2_0: l2-cache { 51 compatible = "cache"; 52 cache-level = <2>; 53 cache-unified; 54 }; 55 }; 56 57 CPU1: cpu@1 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo260"; 60 reg = <0x0 0x1>; 61 clocks = <&cpufreq_hw 0>; 62 capacity-dmips-mhz = <1024>; 63 dynamic-power-coefficient = <100>; 64 enable-method = "psci"; 65 next-level-cache = <&L2_0>; 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 }; 68 69 CPU2: cpu@2 { 70 device_type = "cpu"; 71 compatible = "qcom,kryo260"; 72 reg = <0x0 0x2>; 73 clocks = <&cpufreq_hw 0>; 74 capacity-dmips-mhz = <1024>; 75 dynamic-power-coefficient = <100>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_0>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 }; 80 81 CPU3: cpu@3 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo260"; 84 reg = <0x0 0x3>; 85 clocks = <&cpufreq_hw 0>; 86 capacity-dmips-mhz = <1024>; 87 dynamic-power-coefficient = <100>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_0>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 }; 92 93 CPU4: cpu@100 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo260"; 96 reg = <0x0 0x100>; 97 clocks = <&cpufreq_hw 1>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <1638>; 100 dynamic-power-coefficient = <282>; 101 next-level-cache = <&L2_1>; 102 qcom,freq-domain = <&cpufreq_hw 1>; 103 L2_1: l2-cache { 104 compatible = "cache"; 105 cache-level = <2>; 106 cache-unified; 107 }; 108 }; 109 110 CPU5: cpu@101 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo260"; 113 reg = <0x0 0x101>; 114 clocks = <&cpufreq_hw 1>; 115 capacity-dmips-mhz = <1638>; 116 dynamic-power-coefficient = <282>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_1>; 119 qcom,freq-domain = <&cpufreq_hw 1>; 120 }; 121 122 CPU6: cpu@102 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo260"; 125 reg = <0x0 0x102>; 126 clocks = <&cpufreq_hw 1>; 127 capacity-dmips-mhz = <1638>; 128 dynamic-power-coefficient = <282>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_1>; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 }; 133 134 CPU7: cpu@103 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo260"; 137 reg = <0x0 0x103>; 138 clocks = <&cpufreq_hw 1>; 139 capacity-dmips-mhz = <1638>; 140 dynamic-power-coefficient = <282>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_1>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 }; 145 146 cpu-map { 147 cluster0 { 148 core0 { 149 cpu = <&CPU0>; 150 }; 151 152 core1 { 153 cpu = <&CPU1>; 154 }; 155 156 core2 { 157 cpu = <&CPU2>; 158 }; 159 160 core3 { 161 cpu = <&CPU3>; 162 }; 163 }; 164 165 cluster1 { 166 core0 { 167 cpu = <&CPU4>; 168 }; 169 170 core1 { 171 cpu = <&CPU5>; 172 }; 173 174 core2 { 175 cpu = <&CPU6>; 176 }; 177 178 core3 { 179 cpu = <&CPU7>; 180 }; 181 }; 182 }; 183 }; 184 185 firmware { 186 scm: scm { 187 compatible = "qcom,scm-sm6115", "qcom,scm"; 188 #reset-cells = <1>; 189 }; 190 }; 191 192 memory@80000000 { 193 device_type = "memory"; 194 /* We expect the bootloader to fill in the size */ 195 reg = <0 0x80000000 0 0>; 196 }; 197 198 pmu { 199 compatible = "arm,armv8-pmuv3"; 200 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 201 }; 202 203 psci { 204 compatible = "arm,psci-1.0"; 205 method = "smc"; 206 }; 207 208 reserved_memory: reserved-memory { 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges; 212 213 hyp_mem: memory@45700000 { 214 reg = <0x0 0x45700000 0x0 0x600000>; 215 no-map; 216 }; 217 218 xbl_aop_mem: memory@45e00000 { 219 reg = <0x0 0x45e00000 0x0 0x140000>; 220 no-map; 221 }; 222 223 sec_apps_mem: memory@45fff000 { 224 reg = <0x0 0x45fff000 0x0 0x1000>; 225 no-map; 226 }; 227 228 smem_mem: memory@46000000 { 229 compatible = "qcom,smem"; 230 reg = <0x0 0x46000000 0x0 0x200000>; 231 no-map; 232 233 hwlocks = <&tcsr_mutex 3>; 234 qcom,rpm-msg-ram = <&rpm_msg_ram>; 235 }; 236 237 cdsp_sec_mem: memory@46200000 { 238 reg = <0x0 0x46200000 0x0 0x1e00000>; 239 no-map; 240 }; 241 242 pil_modem_mem: memory@4ab00000 { 243 reg = <0x0 0x4ab00000 0x0 0x6900000>; 244 no-map; 245 }; 246 247 pil_video_mem: memory@51400000 { 248 reg = <0x0 0x51400000 0x0 0x500000>; 249 no-map; 250 }; 251 252 wlan_msa_mem: memory@51900000 { 253 reg = <0x0 0x51900000 0x0 0x100000>; 254 no-map; 255 }; 256 257 pil_cdsp_mem: memory@51a00000 { 258 reg = <0x0 0x51a00000 0x0 0x1e00000>; 259 no-map; 260 }; 261 262 pil_adsp_mem: memory@53800000 { 263 reg = <0x0 0x53800000 0x0 0x2800000>; 264 no-map; 265 }; 266 267 pil_ipa_fw_mem: memory@56100000 { 268 reg = <0x0 0x56100000 0x0 0x10000>; 269 no-map; 270 }; 271 272 pil_ipa_gsi_mem: memory@56110000 { 273 reg = <0x0 0x56110000 0x0 0x5000>; 274 no-map; 275 }; 276 277 pil_gpu_mem: memory@56115000 { 278 reg = <0x0 0x56115000 0x0 0x2000>; 279 no-map; 280 }; 281 282 cont_splash_memory: memory@5c000000 { 283 reg = <0x0 0x5c000000 0x0 0x00f00000>; 284 no-map; 285 }; 286 287 dfps_data_memory: memory@5cf00000 { 288 reg = <0x0 0x5cf00000 0x0 0x0100000>; 289 no-map; 290 }; 291 292 removed_mem: memory@60000000 { 293 reg = <0x0 0x60000000 0x0 0x3900000>; 294 no-map; 295 }; 296 297 rmtfs_mem: memory@89b01000 { 298 compatible = "qcom,rmtfs-mem"; 299 reg = <0x0 0x89b01000 0x0 0x200000>; 300 no-map; 301 302 qcom,client-id = <1>; 303 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 304 }; 305 }; 306 307 rpm-glink { 308 compatible = "qcom,glink-rpm"; 309 310 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 311 qcom,rpm-msg-ram = <&rpm_msg_ram>; 312 mboxes = <&apcs_glb 0>; 313 314 rpm_requests: rpm-requests { 315 compatible = "qcom,rpm-sm6115"; 316 qcom,glink-channels = "rpm_requests"; 317 318 rpmcc: clock-controller { 319 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 320 clocks = <&xo_board>; 321 clock-names = "xo"; 322 #clock-cells = <1>; 323 }; 324 325 rpmpd: power-controller { 326 compatible = "qcom,sm6115-rpmpd"; 327 #power-domain-cells = <1>; 328 operating-points-v2 = <&rpmpd_opp_table>; 329 330 rpmpd_opp_table: opp-table { 331 compatible = "operating-points-v2"; 332 333 rpmpd_opp_min_svs: opp1 { 334 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 335 }; 336 337 rpmpd_opp_low_svs: opp2 { 338 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 339 }; 340 341 rpmpd_opp_svs: opp3 { 342 opp-level = <RPM_SMD_LEVEL_SVS>; 343 }; 344 345 rpmpd_opp_svs_plus: opp4 { 346 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 347 }; 348 349 rpmpd_opp_nom: opp5 { 350 opp-level = <RPM_SMD_LEVEL_NOM>; 351 }; 352 353 rpmpd_opp_nom_plus: opp6 { 354 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 355 }; 356 357 rpmpd_opp_turbo: opp7 { 358 opp-level = <RPM_SMD_LEVEL_TURBO>; 359 }; 360 361 rpmpd_opp_turbo_plus: opp8 { 362 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 363 }; 364 }; 365 }; 366 }; 367 }; 368 369 smp2p-adsp { 370 compatible = "qcom,smp2p"; 371 qcom,smem = <443>, <429>; 372 373 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 374 375 mboxes = <&apcs_glb 10>; 376 377 qcom,local-pid = <0>; 378 qcom,remote-pid = <2>; 379 380 adsp_smp2p_out: master-kernel { 381 qcom,entry-name = "master-kernel"; 382 #qcom,smem-state-cells = <1>; 383 }; 384 385 adsp_smp2p_in: slave-kernel { 386 qcom,entry-name = "slave-kernel"; 387 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 }; 391 }; 392 393 smp2p-cdsp { 394 compatible = "qcom,smp2p"; 395 qcom,smem = <94>, <432>; 396 397 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 398 399 mboxes = <&apcs_glb 30>; 400 401 qcom,local-pid = <0>; 402 qcom,remote-pid = <5>; 403 404 cdsp_smp2p_out: master-kernel { 405 qcom,entry-name = "master-kernel"; 406 #qcom,smem-state-cells = <1>; 407 }; 408 409 cdsp_smp2p_in: slave-kernel { 410 qcom,entry-name = "slave-kernel"; 411 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 }; 415 }; 416 417 smp2p-mpss { 418 compatible = "qcom,smp2p"; 419 qcom,smem = <435>, <428>; 420 421 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 422 423 mboxes = <&apcs_glb 14>; 424 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <1>; 427 428 modem_smp2p_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 modem_smp2p_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 soc: soc@0 { 442 compatible = "simple-bus"; 443 #address-cells = <2>; 444 #size-cells = <2>; 445 ranges = <0 0 0 0 0x10 0>; 446 dma-ranges = <0 0 0 0 0x10 0>; 447 448 tcsr_mutex: hwlock@340000 { 449 compatible = "qcom,tcsr-mutex"; 450 reg = <0x0 0x00340000 0x0 0x20000>; 451 #hwlock-cells = <1>; 452 }; 453 454 tlmm: pinctrl@500000 { 455 compatible = "qcom,sm6115-tlmm"; 456 reg = <0x0 0x00500000 0x0 0x400000>, 457 <0x0 0x00900000 0x0 0x400000>, 458 <0x0 0x00d00000 0x0 0x400000>; 459 reg-names = "west", "south", "east"; 460 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 461 gpio-controller; 462 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 467 qup_i2c0_default: qup-i2c0-default-state { 468 pins = "gpio0", "gpio1"; 469 function = "qup0"; 470 drive-strength = <2>; 471 bias-pull-up; 472 }; 473 474 qup_i2c1_default: qup-i2c1-default-state { 475 pins = "gpio4", "gpio5"; 476 function = "qup1"; 477 drive-strength = <2>; 478 bias-pull-up; 479 }; 480 481 qup_i2c2_default: qup-i2c2-default-state { 482 pins = "gpio6", "gpio7"; 483 function = "qup2"; 484 drive-strength = <2>; 485 bias-pull-up; 486 }; 487 488 qup_i2c3_default: qup-i2c3-default-state { 489 pins = "gpio8", "gpio9"; 490 function = "qup3"; 491 drive-strength = <2>; 492 bias-pull-up; 493 }; 494 495 qup_i2c4_default: qup-i2c4-default-state { 496 pins = "gpio12", "gpio13"; 497 function = "qup4"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 qup_i2c5_default: qup-i2c5-default-state { 503 pins = "gpio14", "gpio15"; 504 function = "qup5"; 505 drive-strength = <2>; 506 bias-pull-up; 507 }; 508 509 qup_spi0_default: qup-spi0-default-state { 510 pins = "gpio0", "gpio1","gpio2", "gpio3"; 511 function = "qup0"; 512 drive-strength = <2>; 513 bias-pull-up; 514 }; 515 516 qup_spi1_default: qup-spi1-default-state { 517 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 518 function = "qup1"; 519 drive-strength = <2>; 520 bias-pull-up; 521 }; 522 523 qup_spi2_default: qup-spi2-default-state { 524 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 525 function = "qup2"; 526 drive-strength = <2>; 527 bias-pull-up; 528 }; 529 530 qup_spi3_default: qup-spi3-default-state { 531 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 532 function = "qup3"; 533 drive-strength = <2>; 534 bias-pull-up; 535 }; 536 537 qup_spi4_default: qup-spi4-default-state { 538 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 539 function = "qup4"; 540 drive-strength = <2>; 541 bias-pull-up; 542 }; 543 544 qup_spi5_default: qup-spi5-default-state { 545 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 546 function = "qup5"; 547 drive-strength = <2>; 548 bias-pull-up; 549 }; 550 551 sdc1_state_on: sdc1-on-state { 552 clk-pins { 553 pins = "sdc1_clk"; 554 bias-disable; 555 drive-strength = <16>; 556 }; 557 558 cmd-pins { 559 pins = "sdc1_cmd"; 560 bias-pull-up; 561 drive-strength = <10>; 562 }; 563 564 data-pins { 565 pins = "sdc1_data"; 566 bias-pull-up; 567 drive-strength = <10>; 568 }; 569 570 rclk-pins { 571 pins = "sdc1_rclk"; 572 bias-pull-down; 573 }; 574 }; 575 576 sdc1_state_off: sdc1-off-state { 577 clk-pins { 578 pins = "sdc1_clk"; 579 bias-disable; 580 drive-strength = <2>; 581 }; 582 583 cmd-pins { 584 pins = "sdc1_cmd"; 585 bias-pull-up; 586 drive-strength = <2>; 587 }; 588 589 data-pins { 590 pins = "sdc1_data"; 591 bias-pull-up; 592 drive-strength = <2>; 593 }; 594 595 rclk-pins { 596 pins = "sdc1_rclk"; 597 bias-pull-down; 598 }; 599 }; 600 601 sdc2_state_on: sdc2-on-state { 602 clk-pins { 603 pins = "sdc2_clk"; 604 bias-disable; 605 drive-strength = <16>; 606 }; 607 608 cmd-pins { 609 pins = "sdc2_cmd"; 610 bias-pull-up; 611 drive-strength = <10>; 612 }; 613 614 data-pins { 615 pins = "sdc2_data"; 616 bias-pull-up; 617 drive-strength = <10>; 618 }; 619 }; 620 621 sdc2_state_off: sdc2-off-state { 622 clk-pins { 623 pins = "sdc2_clk"; 624 bias-disable; 625 drive-strength = <2>; 626 }; 627 628 cmd-pins { 629 pins = "sdc2_cmd"; 630 bias-pull-up; 631 drive-strength = <2>; 632 }; 633 634 data-pins { 635 pins = "sdc2_data"; 636 bias-pull-up; 637 drive-strength = <2>; 638 }; 639 }; 640 }; 641 642 gcc: clock-controller@1400000 { 643 compatible = "qcom,gcc-sm6115"; 644 reg = <0x0 0x01400000 0x0 0x1f0000>; 645 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 646 clock-names = "bi_tcxo", "sleep_clk"; 647 #clock-cells = <1>; 648 #reset-cells = <1>; 649 #power-domain-cells = <1>; 650 }; 651 652 usb_hsphy: phy@1613000 { 653 compatible = "qcom,sm6115-qusb2-phy"; 654 reg = <0x0 0x01613000 0x0 0x180>; 655 #phy-cells = <0>; 656 657 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 658 clock-names = "cfg_ahb", "ref"; 659 660 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 661 nvmem-cells = <&qusb2_hstx_trim>; 662 663 status = "disabled"; 664 }; 665 666 qfprom@1b40000 { 667 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 668 reg = <0x0 0x01b40000 0x0 0x7000>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 672 qusb2_hstx_trim: hstx-trim@25b { 673 reg = <0x25b 0x1>; 674 bits = <1 4>; 675 }; 676 }; 677 678 rng: rng@1b53000 { 679 compatible = "qcom,prng-ee"; 680 reg = <0x0 0x01b53000 0x0 0x1000>; 681 clocks = <&gcc GCC_PRNG_AHB_CLK>; 682 clock-names = "core"; 683 }; 684 685 spmi_bus: spmi@1c40000 { 686 compatible = "qcom,spmi-pmic-arb"; 687 reg = <0x0 0x01c40000 0x0 0x1100>, 688 <0x0 0x01e00000 0x0 0x2000000>, 689 <0x0 0x03e00000 0x0 0x100000>, 690 <0x0 0x03f00000 0x0 0xa0000>, 691 <0x0 0x01c0a000 0x0 0x26000>; 692 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 693 interrupt-names = "periph_irq"; 694 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 695 qcom,ee = <0>; 696 qcom,channel = <0>; 697 #address-cells = <2>; 698 #size-cells = <0>; 699 interrupt-controller; 700 #interrupt-cells = <4>; 701 }; 702 703 tsens0: thermal-sensor@4410000 { 704 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 705 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 706 <0x0 0x04410000 0x0 0x8>; /* SROT */ 707 #qcom,sensors = <16>; 708 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 710 interrupt-names = "uplow", "critical"; 711 #thermal-sensor-cells = <1>; 712 }; 713 714 rpm_msg_ram: sram@45f0000 { 715 compatible = "qcom,rpm-msg-ram"; 716 reg = <0x0 0x045f0000 0x0 0x7000>; 717 }; 718 719 sram@4690000 { 720 compatible = "qcom,rpm-stats"; 721 reg = <0x0 0x04690000 0x0 0x10000>; 722 }; 723 724 sdhc_1: mmc@4744000 { 725 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 726 reg = <0x0 0x04744000 0x0 0x1000>, 727 <0x0 0x04745000 0x0 0x1000>, 728 <0x0 0x04748000 0x0 0x8000>; 729 reg-names = "hc", "cqhci", "ice"; 730 731 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "hc_irq", "pwr_irq"; 734 735 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 736 <&gcc GCC_SDCC1_APPS_CLK>, 737 <&rpmcc RPM_SMD_XO_CLK_SRC>, 738 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 739 clock-names = "iface", "core", "xo", "ice"; 740 741 bus-width = <8>; 742 status = "disabled"; 743 }; 744 745 sdhc_2: mmc@4784000 { 746 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 747 reg = <0x0 0x04784000 0x0 0x1000>; 748 reg-names = "hc"; 749 750 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 752 interrupt-names = "hc_irq", "pwr_irq"; 753 754 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 755 <&gcc GCC_SDCC2_APPS_CLK>, 756 <&rpmcc RPM_SMD_XO_CLK_SRC>; 757 clock-names = "iface", "core", "xo"; 758 759 power-domains = <&rpmpd SM6115_VDDCX>; 760 operating-points-v2 = <&sdhc2_opp_table>; 761 iommus = <&apps_smmu 0x00a0 0x0>; 762 resets = <&gcc GCC_SDCC2_BCR>; 763 764 bus-width = <4>; 765 qcom,dll-config = <0x0007642c>; 766 qcom,ddr-config = <0x80040868>; 767 status = "disabled"; 768 769 sdhc2_opp_table: opp-table { 770 compatible = "operating-points-v2"; 771 772 opp-100000000 { 773 opp-hz = /bits/ 64 <100000000>; 774 required-opps = <&rpmpd_opp_low_svs>; 775 }; 776 777 opp-202000000 { 778 opp-hz = /bits/ 64 <202000000>; 779 required-opps = <&rpmpd_opp_nom>; 780 }; 781 }; 782 }; 783 784 ufs_mem_hc: ufs@4804000 { 785 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 786 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 787 reg-names = "std", "ice"; 788 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 789 phys = <&ufs_mem_phy_lanes>; 790 phy-names = "ufsphy"; 791 lanes-per-direction = <1>; 792 #reset-cells = <1>; 793 resets = <&gcc GCC_UFS_PHY_BCR>; 794 reset-names = "rst"; 795 796 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 797 iommus = <&apps_smmu 0x100 0>; 798 799 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 800 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 801 <&gcc GCC_UFS_PHY_AHB_CLK>, 802 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 803 <&rpmcc RPM_SMD_XO_CLK_SRC>, 804 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 805 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 806 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 807 clock-names = "core_clk", 808 "bus_aggr_clk", 809 "iface_clk", 810 "core_clk_unipro", 811 "ref_clk", 812 "tx_lane0_sync_clk", 813 "rx_lane0_sync_clk", 814 "ice_core_clk"; 815 816 freq-table-hz = <50000000 200000000>, 817 <0 0>, 818 <0 0>, 819 <37500000 150000000>, 820 <0 0>, 821 <0 0>, 822 <0 0>, 823 <75000000 300000000>; 824 825 status = "disabled"; 826 }; 827 828 ufs_mem_phy: phy@4807000 { 829 compatible = "qcom,sm6115-qmp-ufs-phy"; 830 reg = <0x0 0x04807000 0x0 0x1c4>; 831 #address-cells = <2>; 832 #size-cells = <2>; 833 ranges; 834 835 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 836 clock-names = "ref", "ref_aux"; 837 838 resets = <&ufs_mem_hc 0>; 839 reset-names = "ufsphy"; 840 status = "disabled"; 841 842 ufs_mem_phy_lanes: phy@4807400 { 843 reg = <0x0 0x04807400 0x0 0x098>, 844 <0x0 0x04807600 0x0 0x130>, 845 <0x0 0x04807c00 0x0 0x16c>; 846 #phy-cells = <0>; 847 }; 848 }; 849 850 gpi_dma0: dma-controller@4a00000 { 851 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 852 reg = <0x0 0x04a00000 0x0 0x60000>; 853 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 863 dma-channels = <10>; 864 dma-channel-mask = <0xf>; 865 iommus = <&apps_smmu 0xf6 0x0>; 866 #dma-cells = <3>; 867 status = "disabled"; 868 }; 869 870 qupv3_id_0: geniqup@4ac0000 { 871 compatible = "qcom,geni-se-qup"; 872 reg = <0x0 0x04ac0000 0x0 0x2000>; 873 clock-names = "m-ahb", "s-ahb"; 874 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 875 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 876 #address-cells = <2>; 877 #size-cells = <2>; 878 iommus = <&apps_smmu 0xe3 0x0>; 879 ranges; 880 status = "disabled"; 881 882 i2c0: i2c@4a80000 { 883 compatible = "qcom,geni-i2c"; 884 reg = <0x0 0x04a80000 0x0 0x4000>; 885 clock-names = "se"; 886 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&qup_i2c0_default>; 889 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 890 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 891 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 892 dma-names = "tx", "rx"; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 status = "disabled"; 896 }; 897 898 spi0: spi@4a80000 { 899 compatible = "qcom,geni-spi"; 900 reg = <0x0 0x04a80000 0x0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&qup_spi0_default>; 905 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 906 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 907 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 908 dma-names = "tx", "rx"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 i2c1: i2c@4a84000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x0 0x04a84000 0x0 0x4000>; 917 clock-names = "se"; 918 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&qup_i2c1_default>; 921 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 922 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 923 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 924 dma-names = "tx", "rx"; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 status = "disabled"; 928 }; 929 930 spi1: spi@4a84000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0x0 0x04a84000 0x0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_spi1_default>; 937 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 938 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 939 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 940 dma-names = "tx", "rx"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 i2c2: i2c@4a88000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0x0 0x04a88000 0x0 0x4000>; 949 clock-names = "se"; 950 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_i2c2_default>; 953 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 954 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 955 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 956 dma-names = "tx", "rx"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 962 spi2: spi@4a88000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0x0 0x04a88000 0x0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&qup_spi2_default>; 969 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 970 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 971 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 972 dma-names = "tx", "rx"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 }; 977 978 i2c3: i2c@4a8c000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0x0 0x04a8c000 0x0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_i2c3_default>; 985 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 986 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 987 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 988 dma-names = "tx", "rx"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 994 spi3: spi@4a8c000 { 995 compatible = "qcom,geni-spi"; 996 reg = <0x0 0x04a8c000 0x0 0x4000>; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_spi3_default>; 1001 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1002 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1003 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1004 dma-names = "tx", "rx"; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 i2c4: i2c@4a90000 { 1011 compatible = "qcom,geni-i2c"; 1012 reg = <0x0 0x04a90000 0x0 0x4000>; 1013 clock-names = "se"; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&qup_i2c4_default>; 1017 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1018 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1019 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1020 dma-names = "tx", "rx"; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 status = "disabled"; 1024 }; 1025 1026 spi4: spi@4a90000 { 1027 compatible = "qcom,geni-spi"; 1028 reg = <0x0 0x04a90000 0x0 0x4000>; 1029 clock-names = "se"; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_spi4_default>; 1033 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1034 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1035 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1036 dma-names = "tx", "rx"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 uart4: serial@4a90000 { 1043 compatible = "qcom,geni-debug-uart"; 1044 reg = <0x0 0x04a90000 0x0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1047 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1048 status = "disabled"; 1049 }; 1050 1051 i2c5: i2c@4a94000 { 1052 compatible = "qcom,geni-i2c"; 1053 reg = <0x0 0x04a94000 0x0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_i2c5_default>; 1058 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1059 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1060 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1061 dma-names = "tx", "rx"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 spi5: spi@4a94000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0x0 0x04a94000 0x0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_spi5_default>; 1074 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1075 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1076 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1077 dma-names = "tx", "rx"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 }; 1083 1084 usb: usb@4ef8800 { 1085 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1086 reg = <0x0 0x04ef8800 0x0 0x400>; 1087 #address-cells = <2>; 1088 #size-cells = <2>; 1089 ranges; 1090 1091 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1092 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1093 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1094 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1095 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1096 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1097 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1098 1099 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1100 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1101 assigned-clock-rates = <19200000>, <66666667>; 1102 1103 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1105 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1106 1107 resets = <&gcc GCC_USB30_PRIM_BCR>; 1108 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1109 qcom,select-utmi-as-pipe-clk; 1110 status = "disabled"; 1111 1112 usb_dwc3: usb@4e00000 { 1113 compatible = "snps,dwc3"; 1114 reg = <0x0 0x04e00000 0x0 0xcd00>; 1115 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1116 phys = <&usb_hsphy>; 1117 phy-names = "usb2-phy"; 1118 iommus = <&apps_smmu 0x120 0x0>; 1119 snps,dis_u2_susphy_quirk; 1120 snps,dis_enblslpm_quirk; 1121 snps,has-lpm-erratum; 1122 snps,hird-threshold = /bits/ 8 <0x10>; 1123 snps,usb3_lpm_capable; 1124 }; 1125 }; 1126 1127 gpucc: clock-controller@5990000 { 1128 compatible = "qcom,sm6115-gpucc"; 1129 reg = <0x0 0x05990000 0x0 0x9000>; 1130 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1131 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1132 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1133 #clock-cells = <1>; 1134 #reset-cells = <1>; 1135 #power-domain-cells = <1>; 1136 }; 1137 1138 adreno_smmu: iommu@59a0000 { 1139 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1140 "qcom,smmu-500", "arm,mmu-500"; 1141 reg = <0x0 0x059a0000 0x0 0x10000>; 1142 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1151 1152 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1153 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1154 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1155 clock-names = "mem", 1156 "hlos", 1157 "iface"; 1158 power-domains = <&gpucc GPU_CX_GDSC>; 1159 1160 #global-interrupts = <1>; 1161 #iommu-cells = <2>; 1162 }; 1163 1164 mdss: display-subsystem@5e00000 { 1165 compatible = "qcom,sm6115-mdss"; 1166 reg = <0x0 0x05e00000 0x0 0x1000>; 1167 reg-names = "mdss"; 1168 1169 power-domains = <&dispcc MDSS_GDSC>; 1170 1171 clocks = <&gcc GCC_DISP_AHB_CLK>, 1172 <&gcc GCC_DISP_HF_AXI_CLK>, 1173 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1174 1175 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1176 interrupt-controller; 1177 #interrupt-cells = <1>; 1178 1179 iommus = <&apps_smmu 0x420 0x2>, 1180 <&apps_smmu 0x421 0x0>; 1181 1182 #address-cells = <2>; 1183 #size-cells = <2>; 1184 ranges; 1185 1186 status = "disabled"; 1187 1188 mdp: display-controller@5e01000 { 1189 compatible = "qcom,sm6115-dpu"; 1190 reg = <0x0 0x05e01000 0x0 0x8f000>, 1191 <0x0 0x05eb0000 0x0 0x2008>; 1192 reg-names = "mdp", "vbif"; 1193 1194 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1195 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1196 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1197 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1198 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1199 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1200 clock-names = "bus", 1201 "iface", 1202 "core", 1203 "lut", 1204 "rot", 1205 "vsync"; 1206 1207 operating-points-v2 = <&mdp_opp_table>; 1208 power-domains = <&rpmpd SM6115_VDDCX>; 1209 1210 interrupt-parent = <&mdss>; 1211 interrupts = <0>; 1212 1213 ports { 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 1217 port@0 { 1218 reg = <0>; 1219 dpu_intf1_out: endpoint { 1220 remote-endpoint = <&mdss_dsi0_in>; 1221 }; 1222 }; 1223 }; 1224 1225 mdp_opp_table: opp-table { 1226 compatible = "operating-points-v2"; 1227 1228 opp-19200000 { 1229 opp-hz = /bits/ 64 <19200000>; 1230 required-opps = <&rpmpd_opp_min_svs>; 1231 }; 1232 1233 opp-192000000 { 1234 opp-hz = /bits/ 64 <192000000>; 1235 required-opps = <&rpmpd_opp_low_svs>; 1236 }; 1237 1238 opp-256000000 { 1239 opp-hz = /bits/ 64 <256000000>; 1240 required-opps = <&rpmpd_opp_svs>; 1241 }; 1242 1243 opp-307200000 { 1244 opp-hz = /bits/ 64 <307200000>; 1245 required-opps = <&rpmpd_opp_svs_plus>; 1246 }; 1247 1248 opp-384000000 { 1249 opp-hz = /bits/ 64 <384000000>; 1250 required-opps = <&rpmpd_opp_nom>; 1251 }; 1252 }; 1253 }; 1254 1255 mdss_dsi0: dsi@5e94000 { 1256 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1257 reg = <0x0 0x05e94000 0x0 0x400>; 1258 reg-names = "dsi_ctrl"; 1259 1260 interrupt-parent = <&mdss>; 1261 interrupts = <4>; 1262 1263 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1264 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1265 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1266 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1267 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1268 <&gcc GCC_DISP_HF_AXI_CLK>; 1269 clock-names = "byte", 1270 "byte_intf", 1271 "pixel", 1272 "core", 1273 "iface", 1274 "bus"; 1275 1276 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1277 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1278 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1279 1280 operating-points-v2 = <&dsi_opp_table>; 1281 power-domains = <&rpmpd SM6115_VDDCX>; 1282 phys = <&mdss_dsi0_phy>; 1283 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 status = "disabled"; 1288 1289 ports { 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 port@0 { 1294 reg = <0>; 1295 mdss_dsi0_in: endpoint { 1296 remote-endpoint = <&dpu_intf1_out>; 1297 }; 1298 }; 1299 1300 port@1 { 1301 reg = <1>; 1302 mdss_dsi0_out: endpoint { 1303 }; 1304 }; 1305 }; 1306 1307 dsi_opp_table: opp-table { 1308 compatible = "operating-points-v2"; 1309 1310 opp-19200000 { 1311 opp-hz = /bits/ 64 <19200000>; 1312 required-opps = <&rpmpd_opp_min_svs>; 1313 }; 1314 1315 opp-164000000 { 1316 opp-hz = /bits/ 64 <164000000>; 1317 required-opps = <&rpmpd_opp_low_svs>; 1318 }; 1319 1320 opp-187500000 { 1321 opp-hz = /bits/ 64 <187500000>; 1322 required-opps = <&rpmpd_opp_svs>; 1323 }; 1324 }; 1325 }; 1326 1327 mdss_dsi0_phy: phy@5e94400 { 1328 compatible = "qcom,dsi-phy-14nm-2290"; 1329 reg = <0x0 0x05e94400 0x0 0x100>, 1330 <0x0 0x05e94500 0x0 0x300>, 1331 <0x0 0x05e94800 0x0 0x188>; 1332 reg-names = "dsi_phy", 1333 "dsi_phy_lane", 1334 "dsi_pll"; 1335 1336 #clock-cells = <1>; 1337 #phy-cells = <0>; 1338 1339 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1340 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1341 clock-names = "iface", "ref"; 1342 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 dispcc: clock-controller@5f00000 { 1348 compatible = "qcom,sm6115-dispcc"; 1349 reg = <0x0 0x05f00000 0 0x20000>; 1350 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1351 <&sleep_clk>, 1352 <&mdss_dsi0_phy 0>, 1353 <&mdss_dsi0_phy 1>, 1354 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1355 #clock-cells = <1>; 1356 #reset-cells = <1>; 1357 #power-domain-cells = <1>; 1358 }; 1359 1360 remoteproc_mpss: remoteproc@6080000 { 1361 compatible = "qcom,sm6115-mpss-pas"; 1362 reg = <0x0 0x06080000 0x0 0x100>; 1363 1364 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1365 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1366 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1367 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1368 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1369 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1370 interrupt-names = "wdog", "fatal", "ready", "handover", 1371 "stop-ack", "shutdown-ack"; 1372 1373 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1374 clock-names = "xo"; 1375 1376 power-domains = <&rpmpd SM6115_VDDCX>; 1377 1378 memory-region = <&pil_modem_mem>; 1379 1380 qcom,smem-states = <&modem_smp2p_out 0>; 1381 qcom,smem-state-names = "stop"; 1382 1383 status = "disabled"; 1384 1385 glink-edge { 1386 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1387 label = "mpss"; 1388 qcom,remote-pid = <1>; 1389 mboxes = <&apcs_glb 12>; 1390 }; 1391 }; 1392 1393 stm@8002000 { 1394 compatible = "arm,coresight-stm", "arm,primecell"; 1395 reg = <0x0 0x08002000 0x0 0x1000>, 1396 <0x0 0x0e280000 0x0 0x180000>; 1397 reg-names = "stm-base", "stm-stimulus-base"; 1398 1399 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1400 clock-names = "apb_pclk"; 1401 1402 status = "disabled"; 1403 1404 out-ports { 1405 port { 1406 stm_out: endpoint { 1407 remote-endpoint = <&funnel_in0_in>; 1408 }; 1409 }; 1410 }; 1411 }; 1412 1413 cti0: cti@8010000 { 1414 compatible = "arm,coresight-cti", "arm,primecell"; 1415 reg = <0x0 0x08010000 0x0 0x1000>; 1416 1417 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1418 clock-names = "apb_pclk"; 1419 1420 status = "disabled"; 1421 }; 1422 1423 cti1: cti@8011000 { 1424 compatible = "arm,coresight-cti", "arm,primecell"; 1425 reg = <0x0 0x08011000 0x0 0x1000>; 1426 1427 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1428 clock-names = "apb_pclk"; 1429 1430 status = "disabled"; 1431 }; 1432 1433 cti2: cti@8012000 { 1434 compatible = "arm,coresight-cti", "arm,primecell"; 1435 reg = <0x0 0x08012000 0x0 0x1000>; 1436 1437 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1438 clock-names = "apb_pclk"; 1439 1440 status = "disabled"; 1441 }; 1442 1443 cti3: cti@8013000 { 1444 compatible = "arm,coresight-cti", "arm,primecell"; 1445 reg = <0x0 0x08013000 0x0 0x1000>; 1446 1447 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1448 clock-names = "apb_pclk"; 1449 1450 status = "disabled"; 1451 }; 1452 1453 cti4: cti@8014000 { 1454 compatible = "arm,coresight-cti", "arm,primecell"; 1455 reg = <0x0 0x08014000 0x0 0x1000>; 1456 1457 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1458 clock-names = "apb_pclk"; 1459 1460 status = "disabled"; 1461 }; 1462 1463 cti5: cti@8015000 { 1464 compatible = "arm,coresight-cti", "arm,primecell"; 1465 reg = <0x0 0x08015000 0x0 0x1000>; 1466 1467 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1468 clock-names = "apb_pclk"; 1469 1470 status = "disabled"; 1471 }; 1472 1473 cti6: cti@8016000 { 1474 compatible = "arm,coresight-cti", "arm,primecell"; 1475 reg = <0x0 0x08016000 0x0 0x1000>; 1476 1477 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1478 clock-names = "apb_pclk"; 1479 1480 status = "disabled"; 1481 }; 1482 1483 cti7: cti@8017000 { 1484 compatible = "arm,coresight-cti", "arm,primecell"; 1485 reg = <0x0 0x08017000 0x0 0x1000>; 1486 1487 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1488 clock-names = "apb_pclk"; 1489 1490 status = "disabled"; 1491 }; 1492 1493 cti8: cti@8018000 { 1494 compatible = "arm,coresight-cti", "arm,primecell"; 1495 reg = <0x0 0x08018000 0x0 0x1000>; 1496 1497 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1498 clock-names = "apb_pclk"; 1499 1500 status = "disabled"; 1501 }; 1502 1503 cti9: cti@8019000 { 1504 compatible = "arm,coresight-cti", "arm,primecell"; 1505 reg = <0x0 0x08019000 0x0 0x1000>; 1506 1507 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1508 clock-names = "apb_pclk"; 1509 1510 status = "disabled"; 1511 }; 1512 1513 cti10: cti@801a000 { 1514 compatible = "arm,coresight-cti", "arm,primecell"; 1515 reg = <0x0 0x0801a000 0x0 0x1000>; 1516 1517 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1518 clock-names = "apb_pclk"; 1519 1520 status = "disabled"; 1521 }; 1522 1523 cti11: cti@801b000 { 1524 compatible = "arm,coresight-cti", "arm,primecell"; 1525 reg = <0x0 0x0801b000 0x0 0x1000>; 1526 1527 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1528 clock-names = "apb_pclk"; 1529 1530 status = "disabled"; 1531 }; 1532 1533 cti12: cti@801c000 { 1534 compatible = "arm,coresight-cti", "arm,primecell"; 1535 reg = <0x0 0x0801c000 0x0 0x1000>; 1536 1537 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1538 clock-names = "apb_pclk"; 1539 1540 status = "disabled"; 1541 }; 1542 1543 cti13: cti@801d000 { 1544 compatible = "arm,coresight-cti", "arm,primecell"; 1545 reg = <0x0 0x0801d000 0x0 0x1000>; 1546 1547 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1548 clock-names = "apb_pclk"; 1549 1550 status = "disabled"; 1551 }; 1552 1553 cti14: cti@801e000 { 1554 compatible = "arm,coresight-cti", "arm,primecell"; 1555 reg = <0x0 0x0801e000 0x0 0x1000>; 1556 1557 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1558 clock-names = "apb_pclk"; 1559 1560 status = "disabled"; 1561 }; 1562 1563 cti15: cti@801f000 { 1564 compatible = "arm,coresight-cti", "arm,primecell"; 1565 reg = <0x0 0x0801f000 0x0 0x1000>; 1566 1567 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1568 clock-names = "apb_pclk"; 1569 1570 status = "disabled"; 1571 }; 1572 1573 replicator@8046000 { 1574 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1575 reg = <0x0 0x08046000 0x0 0x1000>; 1576 1577 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1578 clock-names = "apb_pclk"; 1579 1580 status = "disabled"; 1581 1582 out-ports { 1583 port { 1584 replicator_out: endpoint { 1585 remote-endpoint = <&etr_in>; 1586 }; 1587 }; 1588 }; 1589 1590 in-ports { 1591 port { 1592 replicator_in: endpoint { 1593 remote-endpoint = <&etf_out>; 1594 }; 1595 }; 1596 }; 1597 }; 1598 1599 etf@8047000 { 1600 compatible = "arm,coresight-tmc", "arm,primecell"; 1601 reg = <0x0 0x08047000 0x0 0x1000>; 1602 1603 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1604 clock-names = "apb_pclk"; 1605 1606 status = "disabled"; 1607 1608 in-ports { 1609 port { 1610 etf_in: endpoint { 1611 remote-endpoint = <&merge_funnel_out>; 1612 }; 1613 }; 1614 }; 1615 1616 out-ports { 1617 port { 1618 etf_out: endpoint { 1619 remote-endpoint = <&replicator_in>; 1620 }; 1621 }; 1622 }; 1623 }; 1624 1625 etr@8048000 { 1626 compatible = "arm,coresight-tmc", "arm,primecell"; 1627 reg = <0x0 0x08048000 0x0 0x1000>; 1628 1629 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1630 clock-names = "apb_pclk"; 1631 1632 status = "disabled"; 1633 1634 in-ports { 1635 port { 1636 etr_in: endpoint { 1637 remote-endpoint = <&replicator_out>; 1638 }; 1639 }; 1640 }; 1641 }; 1642 1643 funnel@8041000 { 1644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1645 reg = <0x0 0x08041000 0x0 0x1000>; 1646 1647 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1648 clock-names = "apb_pclk"; 1649 1650 status = "disabled"; 1651 1652 out-ports { 1653 port { 1654 funnel_in0_out: endpoint { 1655 remote-endpoint = <&merge_funnel_in0>; 1656 }; 1657 }; 1658 }; 1659 1660 in-ports { 1661 port { 1662 funnel_in0_in: endpoint { 1663 remote-endpoint = <&stm_out>; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 funnel@8042000 { 1670 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1671 reg = <0x0 0x08042000 0x0 0x1000>; 1672 1673 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1674 clock-names = "apb_pclk"; 1675 1676 status = "disabled"; 1677 1678 out-ports { 1679 port { 1680 funnel_in1_out: endpoint { 1681 remote-endpoint = <&merge_funnel_in1>; 1682 }; 1683 }; 1684 }; 1685 1686 in-ports { 1687 port { 1688 funnel_in1_in: endpoint { 1689 remote-endpoint = <&funnel_apss1_out>; 1690 }; 1691 }; 1692 }; 1693 }; 1694 1695 funnel@8045000 { 1696 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1697 reg = <0x0 0x08045000 0x0 0x1000>; 1698 1699 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1700 clock-names = "apb_pclk"; 1701 1702 status = "disabled"; 1703 1704 out-ports { 1705 port { 1706 merge_funnel_out: endpoint { 1707 remote-endpoint = <&etf_in>; 1708 }; 1709 }; 1710 }; 1711 1712 in-ports { 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 1716 port@0 { 1717 reg = <0>; 1718 merge_funnel_in0: endpoint { 1719 remote-endpoint = <&funnel_in0_out>; 1720 }; 1721 }; 1722 1723 port@1 { 1724 reg = <1>; 1725 merge_funnel_in1: endpoint { 1726 remote-endpoint = <&funnel_in1_out>; 1727 }; 1728 }; 1729 }; 1730 }; 1731 1732 etm@9040000 { 1733 compatible = "arm,coresight-etm4x", "arm,primecell"; 1734 reg = <0x0 0x09040000 0x0 0x1000>; 1735 1736 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1737 clock-names = "apb_pclk"; 1738 arm,coresight-loses-context-with-cpu; 1739 1740 cpu = <&CPU0>; 1741 1742 status = "disabled"; 1743 1744 out-ports { 1745 port { 1746 etm0_out: endpoint { 1747 remote-endpoint = <&funnel_apss0_in0>; 1748 }; 1749 }; 1750 }; 1751 }; 1752 1753 etm@9140000 { 1754 compatible = "arm,coresight-etm4x", "arm,primecell"; 1755 reg = <0x0 0x09140000 0x0 0x1000>; 1756 1757 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1758 clock-names = "apb_pclk"; 1759 arm,coresight-loses-context-with-cpu; 1760 1761 cpu = <&CPU1>; 1762 1763 status = "disabled"; 1764 1765 out-ports { 1766 port { 1767 etm1_out: endpoint { 1768 remote-endpoint = <&funnel_apss0_in1>; 1769 }; 1770 }; 1771 }; 1772 }; 1773 1774 etm@9240000 { 1775 compatible = "arm,coresight-etm4x", "arm,primecell"; 1776 reg = <0x0 0x09240000 0x0 0x1000>; 1777 1778 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1779 clock-names = "apb_pclk"; 1780 arm,coresight-loses-context-with-cpu; 1781 1782 cpu = <&CPU2>; 1783 1784 status = "disabled"; 1785 1786 out-ports { 1787 port { 1788 etm2_out: endpoint { 1789 remote-endpoint = <&funnel_apss0_in2>; 1790 }; 1791 }; 1792 }; 1793 }; 1794 1795 etm@9340000 { 1796 compatible = "arm,coresight-etm4x", "arm,primecell"; 1797 reg = <0x0 0x09340000 0x0 0x1000>; 1798 1799 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1800 clock-names = "apb_pclk"; 1801 arm,coresight-loses-context-with-cpu; 1802 1803 cpu = <&CPU3>; 1804 1805 status = "disabled"; 1806 1807 out-ports { 1808 port { 1809 etm3_out: endpoint { 1810 remote-endpoint = <&funnel_apss0_in3>; 1811 }; 1812 }; 1813 }; 1814 }; 1815 1816 etm@9440000 { 1817 compatible = "arm,coresight-etm4x", "arm,primecell"; 1818 reg = <0x0 0x09440000 0x0 0x1000>; 1819 1820 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1821 clock-names = "apb_pclk"; 1822 arm,coresight-loses-context-with-cpu; 1823 1824 cpu = <&CPU4>; 1825 1826 status = "disabled"; 1827 1828 out-ports { 1829 port { 1830 etm4_out: endpoint { 1831 remote-endpoint = <&funnel_apss0_in4>; 1832 }; 1833 }; 1834 }; 1835 }; 1836 1837 etm@9540000 { 1838 compatible = "arm,coresight-etm4x", "arm,primecell"; 1839 reg = <0x0 0x09540000 0x0 0x1000>; 1840 1841 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1842 clock-names = "apb_pclk"; 1843 arm,coresight-loses-context-with-cpu; 1844 1845 cpu = <&CPU5>; 1846 1847 status = "disabled"; 1848 1849 out-ports { 1850 port { 1851 etm5_out: endpoint { 1852 remote-endpoint = <&funnel_apss0_in5>; 1853 }; 1854 }; 1855 }; 1856 }; 1857 1858 etm@9640000 { 1859 compatible = "arm,coresight-etm4x", "arm,primecell"; 1860 reg = <0x0 0x09640000 0x0 0x1000>; 1861 1862 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1863 clock-names = "apb_pclk"; 1864 arm,coresight-loses-context-with-cpu; 1865 1866 cpu = <&CPU6>; 1867 1868 status = "disabled"; 1869 1870 out-ports { 1871 port { 1872 etm6_out: endpoint { 1873 remote-endpoint = <&funnel_apss0_in6>; 1874 }; 1875 }; 1876 }; 1877 }; 1878 1879 etm@9740000 { 1880 compatible = "arm,coresight-etm4x", "arm,primecell"; 1881 reg = <0x0 0x09740000 0x0 0x1000>; 1882 1883 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1884 clock-names = "apb_pclk"; 1885 arm,coresight-loses-context-with-cpu; 1886 1887 cpu = <&CPU7>; 1888 1889 status = "disabled"; 1890 1891 out-ports { 1892 port { 1893 etm7_out: endpoint { 1894 remote-endpoint = <&funnel_apss0_in7>; 1895 }; 1896 }; 1897 }; 1898 }; 1899 1900 funnel@9800000 { 1901 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1902 reg = <0x0 0x09800000 0x0 0x1000>; 1903 1904 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1905 clock-names = "apb_pclk"; 1906 1907 status = "disabled"; 1908 1909 out-ports { 1910 port { 1911 funnel_apss0_out: endpoint { 1912 remote-endpoint = <&funnel_apss1_in>; 1913 }; 1914 }; 1915 }; 1916 1917 in-ports { 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 1921 port@0 { 1922 reg = <0>; 1923 funnel_apss0_in0: endpoint { 1924 remote-endpoint = <&etm0_out>; 1925 }; 1926 }; 1927 1928 port@1 { 1929 reg = <1>; 1930 funnel_apss0_in1: endpoint { 1931 remote-endpoint = <&etm1_out>; 1932 }; 1933 }; 1934 1935 port@2 { 1936 reg = <2>; 1937 funnel_apss0_in2: endpoint { 1938 remote-endpoint = <&etm2_out>; 1939 }; 1940 }; 1941 1942 port@3 { 1943 reg = <3>; 1944 funnel_apss0_in3: endpoint { 1945 remote-endpoint = <&etm3_out>; 1946 }; 1947 }; 1948 1949 port@4 { 1950 reg = <4>; 1951 funnel_apss0_in4: endpoint { 1952 remote-endpoint = <&etm4_out>; 1953 }; 1954 }; 1955 1956 port@5 { 1957 reg = <5>; 1958 funnel_apss0_in5: endpoint { 1959 remote-endpoint = <&etm5_out>; 1960 }; 1961 }; 1962 1963 port@6 { 1964 reg = <6>; 1965 funnel_apss0_in6: endpoint { 1966 remote-endpoint = <&etm6_out>; 1967 }; 1968 }; 1969 1970 port@7 { 1971 reg = <7>; 1972 funnel_apss0_in7: endpoint { 1973 remote-endpoint = <&etm7_out>; 1974 }; 1975 }; 1976 }; 1977 }; 1978 1979 funnel@9810000 { 1980 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1981 reg = <0x0 0x09810000 0x0 0x1000>; 1982 1983 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1984 clock-names = "apb_pclk"; 1985 1986 status = "disabled"; 1987 1988 out-ports { 1989 port { 1990 funnel_apss1_out: endpoint { 1991 remote-endpoint = <&funnel_in1_in>; 1992 }; 1993 }; 1994 }; 1995 1996 in-ports { 1997 port { 1998 funnel_apss1_in: endpoint { 1999 remote-endpoint = <&funnel_apss0_out>; 2000 }; 2001 }; 2002 }; 2003 }; 2004 2005 remoteproc_adsp: remoteproc@ab00000 { 2006 compatible = "qcom,sm6115-adsp-pas"; 2007 reg = <0x0 0x0ab00000 0x0 0x100>; 2008 2009 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2010 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2011 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2012 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2013 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2014 interrupt-names = "wdog", "fatal", "ready", 2015 "handover", "stop-ack"; 2016 2017 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2018 clock-names = "xo"; 2019 2020 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2021 <&rpmpd SM6115_VDD_LPI_MX>; 2022 2023 memory-region = <&pil_adsp_mem>; 2024 2025 qcom,smem-states = <&adsp_smp2p_out 0>; 2026 qcom,smem-state-names = "stop"; 2027 2028 status = "disabled"; 2029 2030 glink-edge { 2031 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2032 label = "lpass"; 2033 qcom,remote-pid = <2>; 2034 mboxes = <&apcs_glb 8>; 2035 2036 fastrpc { 2037 compatible = "qcom,fastrpc"; 2038 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2039 label = "adsp"; 2040 qcom,non-secure-domain; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 2044 compute-cb@3 { 2045 compatible = "qcom,fastrpc-compute-cb"; 2046 reg = <3>; 2047 iommus = <&apps_smmu 0x01c3 0x0>; 2048 }; 2049 2050 compute-cb@4 { 2051 compatible = "qcom,fastrpc-compute-cb"; 2052 reg = <4>; 2053 iommus = <&apps_smmu 0x01c4 0x0>; 2054 }; 2055 2056 compute-cb@5 { 2057 compatible = "qcom,fastrpc-compute-cb"; 2058 reg = <5>; 2059 iommus = <&apps_smmu 0x01c5 0x0>; 2060 }; 2061 2062 compute-cb@6 { 2063 compatible = "qcom,fastrpc-compute-cb"; 2064 reg = <6>; 2065 iommus = <&apps_smmu 0x01c6 0x0>; 2066 }; 2067 2068 compute-cb@7 { 2069 compatible = "qcom,fastrpc-compute-cb"; 2070 reg = <7>; 2071 iommus = <&apps_smmu 0x01c7 0x0>; 2072 }; 2073 }; 2074 }; 2075 }; 2076 2077 remoteproc_cdsp: remoteproc@b300000 { 2078 compatible = "qcom,sm6115-cdsp-pas"; 2079 reg = <0x0 0x0b300000 0x0 0x100000>; 2080 2081 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2082 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2083 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2084 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2085 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2086 interrupt-names = "wdog", "fatal", "ready", 2087 "handover", "stop-ack"; 2088 2089 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2090 clock-names = "xo"; 2091 2092 power-domains = <&rpmpd SM6115_VDDCX>; 2093 2094 memory-region = <&pil_cdsp_mem>; 2095 2096 qcom,smem-states = <&cdsp_smp2p_out 0>; 2097 qcom,smem-state-names = "stop"; 2098 2099 status = "disabled"; 2100 2101 glink-edge { 2102 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2103 label = "cdsp"; 2104 qcom,remote-pid = <5>; 2105 mboxes = <&apcs_glb 28>; 2106 2107 fastrpc { 2108 compatible = "qcom,fastrpc"; 2109 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2110 label = "cdsp"; 2111 qcom,non-secure-domain; 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 2115 compute-cb@1 { 2116 compatible = "qcom,fastrpc-compute-cb"; 2117 reg = <1>; 2118 iommus = <&apps_smmu 0x0c01 0x0>; 2119 }; 2120 2121 compute-cb@2 { 2122 compatible = "qcom,fastrpc-compute-cb"; 2123 reg = <2>; 2124 iommus = <&apps_smmu 0x0c02 0x0>; 2125 }; 2126 2127 compute-cb@3 { 2128 compatible = "qcom,fastrpc-compute-cb"; 2129 reg = <3>; 2130 iommus = <&apps_smmu 0x0c03 0x0>; 2131 }; 2132 2133 compute-cb@4 { 2134 compatible = "qcom,fastrpc-compute-cb"; 2135 reg = <4>; 2136 iommus = <&apps_smmu 0x0c04 0x0>; 2137 }; 2138 2139 compute-cb@5 { 2140 compatible = "qcom,fastrpc-compute-cb"; 2141 reg = <5>; 2142 iommus = <&apps_smmu 0x0c05 0x0>; 2143 }; 2144 2145 compute-cb@6 { 2146 compatible = "qcom,fastrpc-compute-cb"; 2147 reg = <6>; 2148 iommus = <&apps_smmu 0x0c06 0x0>; 2149 }; 2150 2151 /* note: secure cb9 in downstream */ 2152 }; 2153 }; 2154 }; 2155 2156 apps_smmu: iommu@c600000 { 2157 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2158 reg = <0x0 0x0c600000 0x0 0x80000>; 2159 #iommu-cells = <2>; 2160 #global-interrupts = <1>; 2161 2162 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2227 }; 2228 2229 wifi: wifi@c800000 { 2230 compatible = "qcom,wcn3990-wifi"; 2231 reg = <0x0 0x0c800000 0x0 0x800000>; 2232 reg-names = "membase"; 2233 memory-region = <&wlan_msa_mem>; 2234 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2246 iommus = <&apps_smmu 0x1a0 0x1>; 2247 qcom,msa-fixed-perm; 2248 status = "disabled"; 2249 }; 2250 2251 watchdog@f017000 { 2252 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2253 reg = <0x0 0x0f017000 0x0 0x1000>; 2254 clocks = <&sleep_clk>; 2255 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2256 }; 2257 2258 apcs_glb: mailbox@f111000 { 2259 compatible = "qcom,sm6115-apcs-hmss-global", 2260 "qcom,msm8994-apcs-kpss-global"; 2261 reg = <0x0 0x0f111000 0x0 0x1000>; 2262 2263 #mbox-cells = <1>; 2264 }; 2265 2266 timer@f120000 { 2267 compatible = "arm,armv7-timer-mem"; 2268 reg = <0x0 0x0f120000 0x0 0x1000>; 2269 #address-cells = <2>; 2270 #size-cells = <2>; 2271 ranges; 2272 clock-frequency = <19200000>; 2273 2274 frame@f121000 { 2275 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2276 frame-number = <0>; 2277 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2279 }; 2280 2281 frame@f123000 { 2282 reg = <0x0 0x0f123000 0x0 0x1000>; 2283 frame-number = <1>; 2284 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2285 status = "disabled"; 2286 }; 2287 2288 frame@f124000 { 2289 reg = <0x0 0x0f124000 0x0 0x1000>; 2290 frame-number = <2>; 2291 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2292 status = "disabled"; 2293 }; 2294 2295 frame@f125000 { 2296 reg = <0x0 0x0f125000 0x0 0x1000>; 2297 frame-number = <3>; 2298 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2299 status = "disabled"; 2300 }; 2301 2302 frame@f126000 { 2303 reg = <0x0 0x0f126000 0x0 0x1000>; 2304 frame-number = <4>; 2305 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2306 status = "disabled"; 2307 }; 2308 2309 frame@f127000 { 2310 reg = <0x0 0x0f127000 0x0 0x1000>; 2311 frame-number = <5>; 2312 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2313 status = "disabled"; 2314 }; 2315 2316 frame@f128000 { 2317 reg = <0x0 0x0f128000 0x0 0x1000>; 2318 frame-number = <6>; 2319 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2320 status = "disabled"; 2321 }; 2322 }; 2323 2324 intc: interrupt-controller@f200000 { 2325 compatible = "arm,gic-v3"; 2326 reg = <0x0 0x0f200000 0x0 0x10000>, 2327 <0x0 0x0f300000 0x0 0x100000>; 2328 #interrupt-cells = <3>; 2329 interrupt-controller; 2330 interrupt-parent = <&intc>; 2331 #redistributor-regions = <1>; 2332 redistributor-stride = <0x0 0x20000>; 2333 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2334 }; 2335 2336 cpufreq_hw: cpufreq@f521000 { 2337 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2338 reg = <0x0 0x0f521000 0x0 0x1000>, 2339 <0x0 0x0f523000 0x0 0x1000>; 2340 2341 reg-names = "freq-domain0", "freq-domain1"; 2342 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2343 clock-names = "xo", "alternate"; 2344 2345 #freq-domain-cells = <1>; 2346 #clock-cells = <1>; 2347 }; 2348 }; 2349 2350 thermal-zones { 2351 mapss-thermal { 2352 polling-delay-passive = <0>; 2353 polling-delay = <0>; 2354 thermal-sensors = <&tsens0 0>; 2355 2356 trips { 2357 trip-point0 { 2358 temperature = <115000>; 2359 hysteresis = <5000>; 2360 type = "passive"; 2361 }; 2362 2363 trip-point1 { 2364 temperature = <125000>; 2365 hysteresis = <1000>; 2366 type = "passive"; 2367 }; 2368 }; 2369 }; 2370 2371 cdsp-hvx-thermal { 2372 polling-delay-passive = <0>; 2373 polling-delay = <0>; 2374 thermal-sensors = <&tsens0 1>; 2375 2376 trips { 2377 trip-point0 { 2378 temperature = <115000>; 2379 hysteresis = <5000>; 2380 type = "passive"; 2381 }; 2382 2383 trip-point1 { 2384 temperature = <125000>; 2385 hysteresis = <1000>; 2386 type = "passive"; 2387 }; 2388 }; 2389 }; 2390 2391 wlan-thermal { 2392 polling-delay-passive = <0>; 2393 polling-delay = <0>; 2394 thermal-sensors = <&tsens0 2>; 2395 2396 trips { 2397 trip-point0 { 2398 temperature = <115000>; 2399 hysteresis = <5000>; 2400 type = "passive"; 2401 }; 2402 2403 trip-point1 { 2404 temperature = <125000>; 2405 hysteresis = <1000>; 2406 type = "passive"; 2407 }; 2408 }; 2409 }; 2410 2411 camera-thermal { 2412 polling-delay-passive = <0>; 2413 polling-delay = <0>; 2414 thermal-sensors = <&tsens0 3>; 2415 2416 trips { 2417 trip-point0 { 2418 temperature = <115000>; 2419 hysteresis = <5000>; 2420 type = "passive"; 2421 }; 2422 2423 trip-point1 { 2424 temperature = <125000>; 2425 hysteresis = <1000>; 2426 type = "passive"; 2427 }; 2428 }; 2429 }; 2430 2431 video-thermal { 2432 polling-delay-passive = <0>; 2433 polling-delay = <0>; 2434 thermal-sensors = <&tsens0 4>; 2435 2436 trips { 2437 trip-point0 { 2438 temperature = <115000>; 2439 hysteresis = <5000>; 2440 type = "passive"; 2441 }; 2442 2443 trip-point1 { 2444 temperature = <125000>; 2445 hysteresis = <1000>; 2446 type = "passive"; 2447 }; 2448 }; 2449 }; 2450 2451 modem1-thermal { 2452 polling-delay-passive = <0>; 2453 polling-delay = <0>; 2454 thermal-sensors = <&tsens0 5>; 2455 2456 trips { 2457 trip-point0 { 2458 temperature = <115000>; 2459 hysteresis = <5000>; 2460 type = "passive"; 2461 }; 2462 2463 trip-point1 { 2464 temperature = <125000>; 2465 hysteresis = <1000>; 2466 type = "passive"; 2467 }; 2468 }; 2469 }; 2470 2471 cpu4-thermal { 2472 polling-delay-passive = <0>; 2473 polling-delay = <0>; 2474 thermal-sensors = <&tsens0 6>; 2475 2476 trips { 2477 cpu4_alert0: trip-point0 { 2478 temperature = <90000>; 2479 hysteresis = <2000>; 2480 type = "passive"; 2481 }; 2482 2483 cpu4_alert1: trip-point1 { 2484 temperature = <95000>; 2485 hysteresis = <2000>; 2486 type = "passive"; 2487 }; 2488 2489 cpu4_crit: cpu_crit { 2490 temperature = <110000>; 2491 hysteresis = <1000>; 2492 type = "critical"; 2493 }; 2494 }; 2495 }; 2496 2497 cpu5-thermal { 2498 polling-delay-passive = <0>; 2499 polling-delay = <0>; 2500 thermal-sensors = <&tsens0 7>; 2501 2502 trips { 2503 cpu5_alert0: trip-point0 { 2504 temperature = <90000>; 2505 hysteresis = <2000>; 2506 type = "passive"; 2507 }; 2508 2509 cpu5_alert1: trip-point1 { 2510 temperature = <95000>; 2511 hysteresis = <2000>; 2512 type = "passive"; 2513 }; 2514 2515 cpu5_crit: cpu_crit { 2516 temperature = <110000>; 2517 hysteresis = <1000>; 2518 type = "critical"; 2519 }; 2520 }; 2521 }; 2522 2523 cpu6-thermal { 2524 polling-delay-passive = <0>; 2525 polling-delay = <0>; 2526 thermal-sensors = <&tsens0 8>; 2527 2528 trips { 2529 cpu6_alert0: trip-point0 { 2530 temperature = <90000>; 2531 hysteresis = <2000>; 2532 type = "passive"; 2533 }; 2534 2535 cpu6_alert1: trip-point1 { 2536 temperature = <95000>; 2537 hysteresis = <2000>; 2538 type = "passive"; 2539 }; 2540 2541 cpu6_crit: cpu_crit { 2542 temperature = <110000>; 2543 hysteresis = <1000>; 2544 type = "critical"; 2545 }; 2546 }; 2547 }; 2548 2549 cpu7-thermal { 2550 polling-delay-passive = <0>; 2551 polling-delay = <0>; 2552 thermal-sensors = <&tsens0 9>; 2553 2554 trips { 2555 cpu7_alert0: trip-point0 { 2556 temperature = <90000>; 2557 hysteresis = <2000>; 2558 type = "passive"; 2559 }; 2560 2561 cpu7_alert1: trip-point1 { 2562 temperature = <95000>; 2563 hysteresis = <2000>; 2564 type = "passive"; 2565 }; 2566 2567 cpu7_crit: cpu_crit { 2568 temperature = <110000>; 2569 hysteresis = <1000>; 2570 type = "critical"; 2571 }; 2572 }; 2573 }; 2574 2575 cpu45-thermal { 2576 polling-delay-passive = <0>; 2577 polling-delay = <0>; 2578 thermal-sensors = <&tsens0 10>; 2579 2580 trips { 2581 cpu45_alert0: trip-point0 { 2582 temperature = <90000>; 2583 hysteresis = <2000>; 2584 type = "passive"; 2585 }; 2586 2587 cpu45_alert1: trip-point1 { 2588 temperature = <95000>; 2589 hysteresis = <2000>; 2590 type = "passive"; 2591 }; 2592 2593 cpu45_crit: cpu_crit { 2594 temperature = <110000>; 2595 hysteresis = <1000>; 2596 type = "critical"; 2597 }; 2598 }; 2599 }; 2600 2601 cpu67-thermal { 2602 polling-delay-passive = <0>; 2603 polling-delay = <0>; 2604 thermal-sensors = <&tsens0 11>; 2605 2606 trips { 2607 cpu67_alert0: trip-point0 { 2608 temperature = <90000>; 2609 hysteresis = <2000>; 2610 type = "passive"; 2611 }; 2612 2613 cpu67_alert1: trip-point1 { 2614 temperature = <95000>; 2615 hysteresis = <2000>; 2616 type = "passive"; 2617 }; 2618 2619 cpu67_crit: cpu_crit { 2620 temperature = <110000>; 2621 hysteresis = <1000>; 2622 type = "critical"; 2623 }; 2624 }; 2625 }; 2626 2627 cpu0123-thermal { 2628 polling-delay-passive = <0>; 2629 polling-delay = <0>; 2630 thermal-sensors = <&tsens0 12>; 2631 2632 trips { 2633 cpu0123_alert0: trip-point0 { 2634 temperature = <90000>; 2635 hysteresis = <2000>; 2636 type = "passive"; 2637 }; 2638 2639 cpu0123_alert1: trip-point1 { 2640 temperature = <95000>; 2641 hysteresis = <2000>; 2642 type = "passive"; 2643 }; 2644 2645 cpu0123_crit: cpu_crit { 2646 temperature = <110000>; 2647 hysteresis = <1000>; 2648 type = "critical"; 2649 }; 2650 }; 2651 }; 2652 2653 modem0-thermal { 2654 polling-delay-passive = <0>; 2655 polling-delay = <0>; 2656 thermal-sensors = <&tsens0 13>; 2657 2658 trips { 2659 trip-point0 { 2660 temperature = <115000>; 2661 hysteresis = <5000>; 2662 type = "passive"; 2663 }; 2664 2665 trip-point1 { 2666 temperature = <125000>; 2667 hysteresis = <1000>; 2668 type = "passive"; 2669 }; 2670 }; 2671 }; 2672 2673 display-thermal { 2674 polling-delay-passive = <0>; 2675 polling-delay = <0>; 2676 thermal-sensors = <&tsens0 14>; 2677 2678 trips { 2679 trip-point0 { 2680 temperature = <115000>; 2681 hysteresis = <5000>; 2682 type = "passive"; 2683 }; 2684 2685 trip-point1 { 2686 temperature = <125000>; 2687 hysteresis = <1000>; 2688 type = "passive"; 2689 }; 2690 }; 2691 }; 2692 2693 gpu-thermal { 2694 polling-delay-passive = <0>; 2695 polling-delay = <0>; 2696 thermal-sensors = <&tsens0 15>; 2697 2698 trips { 2699 trip-point0 { 2700 temperature = <115000>; 2701 hysteresis = <5000>; 2702 type = "passive"; 2703 }; 2704 2705 trip-point1 { 2706 temperature = <125000>; 2707 hysteresis = <1000>; 2708 type = "passive"; 2709 }; 2710 }; 2711 }; 2712 }; 2713 2714 timer { 2715 compatible = "arm,armv8-timer"; 2716 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2717 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2718 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2719 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2720 }; 2721}; 2722