1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,qcm2290.h> 16#include <dt-bindings/interconnect/qcom,rpm-icc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 clock-frequency = <32764>; 36 #clock-cells = <0>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x0>; 48 clocks = <&cpufreq_hw 0>; 49 capacity-dmips-mhz = <1024>; 50 dynamic-power-coefficient = <100>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 L2_0: l2-cache { 57 compatible = "cache"; 58 cache-level = <2>; 59 cache-unified; 60 }; 61 }; 62 63 CPU1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0 0x1>; 67 clocks = <&cpufreq_hw 0>; 68 capacity-dmips-mhz = <1024>; 69 dynamic-power-coefficient = <100>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 power-domains = <&CPU_PD1>; 74 power-domain-names = "psci"; 75 }; 76 77 CPU2: cpu@2 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x2>; 81 clocks = <&cpufreq_hw 0>; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 enable-method = "psci"; 85 next-level-cache = <&L2_0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 power-domains = <&CPU_PD2>; 88 power-domain-names = "psci"; 89 }; 90 91 CPU3: cpu@3 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x0 0x3>; 95 clocks = <&cpufreq_hw 0>; 96 capacity-dmips-mhz = <1024>; 97 dynamic-power-coefficient = <100>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_0>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 power-domains = <&CPU_PD3>; 102 power-domain-names = "psci"; 103 }; 104 105 cpu-map { 106 cluster0 { 107 core0 { 108 cpu = <&CPU0>; 109 }; 110 111 core1 { 112 cpu = <&CPU1>; 113 }; 114 115 core2 { 116 cpu = <&CPU2>; 117 }; 118 119 core3 { 120 cpu = <&CPU3>; 121 }; 122 }; 123 }; 124 125 domain-idle-states { 126 CLUSTER_SLEEP: cluster-sleep-0 { 127 compatible = "domain-idle-state"; 128 arm,psci-suspend-param = <0x41000043>; 129 entry-latency-us = <800>; 130 exit-latency-us = <2118>; 131 min-residency-us = <7376>; 132 }; 133 }; 134 135 idle-states { 136 entry-method = "psci"; 137 138 CPU_SLEEP: cpu-sleep-0 { 139 compatible = "arm,idle-state"; 140 idle-state-name = "power-collapse"; 141 arm,psci-suspend-param = <0x40000003>; 142 entry-latency-us = <290>; 143 exit-latency-us = <376>; 144 min-residency-us = <1182>; 145 local-timer-stop; 146 }; 147 }; 148 }; 149 150 firmware { 151 scm: scm { 152 compatible = "qcom,scm-qcm2290", "qcom,scm"; 153 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 154 clock-names = "core"; 155 #reset-cells = <1>; 156 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 157 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 158 }; 159 }; 160 161 memory@40000000 { 162 device_type = "memory"; 163 /* We expect the bootloader to fill in the size */ 164 reg = <0 0x40000000 0 0>; 165 }; 166 167 pmu { 168 compatible = "arm,armv8-pmuv3"; 169 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 176 CPU_PD0: power-domain-cpu0 { 177 #power-domain-cells = <0>; 178 power-domains = <&CLUSTER_PD>; 179 domain-idle-states = <&CPU_SLEEP>; 180 }; 181 182 CPU_PD1: power-domain-cpu1 { 183 #power-domain-cells = <0>; 184 power-domains = <&CLUSTER_PD>; 185 domain-idle-states = <&CPU_SLEEP>; 186 }; 187 188 CPU_PD2: power-domain-cpu2 { 189 #power-domain-cells = <0>; 190 power-domains = <&CLUSTER_PD>; 191 domain-idle-states = <&CPU_SLEEP>; 192 }; 193 194 CPU_PD3: power-domain-cpu3 { 195 #power-domain-cells = <0>; 196 power-domains = <&CLUSTER_PD>; 197 domain-idle-states = <&CPU_SLEEP>; 198 }; 199 200 CLUSTER_PD: power-domain-cpu-cluster { 201 #power-domain-cells = <0>; 202 power-domains = <&mpm>; 203 domain-idle-states = <&CLUSTER_SLEEP>; 204 }; 205 }; 206 207 rpm: remoteproc { 208 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 209 210 glink-edge { 211 compatible = "qcom,glink-rpm"; 212 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 213 qcom,rpm-msg-ram = <&rpm_msg_ram>; 214 mboxes = <&apcs_glb 0>; 215 216 rpm_requests: rpm-requests { 217 compatible = "qcom,rpm-qcm2290"; 218 qcom,glink-channels = "rpm_requests"; 219 220 rpmcc: clock-controller { 221 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 222 clocks = <&xo_board>; 223 clock-names = "xo"; 224 #clock-cells = <1>; 225 }; 226 227 rpmpd: power-controller { 228 compatible = "qcom,qcm2290-rpmpd"; 229 #power-domain-cells = <1>; 230 operating-points-v2 = <&rpmpd_opp_table>; 231 232 rpmpd_opp_table: opp-table { 233 compatible = "operating-points-v2"; 234 235 rpmpd_opp_min_svs: opp1 { 236 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 237 }; 238 239 rpmpd_opp_low_svs: opp2 { 240 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 241 }; 242 243 rpmpd_opp_svs: opp3 { 244 opp-level = <RPM_SMD_LEVEL_SVS>; 245 }; 246 247 rpmpd_opp_svs_plus: opp4 { 248 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 249 }; 250 251 rpmpd_opp_nom: opp5 { 252 opp-level = <RPM_SMD_LEVEL_NOM>; 253 }; 254 255 rpmpd_opp_nom_plus: opp6 { 256 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 257 }; 258 259 rpmpd_opp_turbo: opp7 { 260 opp-level = <RPM_SMD_LEVEL_TURBO>; 261 }; 262 263 rpmpd_opp_turbo_plus: opp8 { 264 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 265 }; 266 }; 267 }; 268 }; 269 }; 270 271 mpm: interrupt-controller { 272 compatible = "qcom,mpm"; 273 qcom,rpm-msg-ram = <&apss_mpm>; 274 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 275 mboxes = <&apcs_glb 1>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 #power-domain-cells = <0>; 279 interrupt-parent = <&intc>; 280 qcom,mpm-pin-count = <96>; 281 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 282 <5 296>, /* Soundwire master_irq */ 283 <12 422>, /* DWC3 ss_phy_irq */ 284 <24 79>, /* Soundwire wake_irq */ 285 <86 183>, /* MPM wake, SPMI */ 286 <90 260>; /* QUSB2_PHY DP+DM */ 287 }; 288 }; 289 290 reserved_memory: reserved-memory { 291 #address-cells = <2>; 292 #size-cells = <2>; 293 ranges; 294 295 hyp_mem: hyp@45700000 { 296 reg = <0x0 0x45700000 0x0 0x600000>; 297 no-map; 298 }; 299 300 xbl_aop_mem: xbl-aop@45e00000 { 301 reg = <0x0 0x45e00000 0x0 0x140000>; 302 no-map; 303 }; 304 305 sec_apps_mem: sec-apps@45fff000 { 306 reg = <0x0 0x45fff000 0x0 0x1000>; 307 no-map; 308 }; 309 310 smem_mem: smem@46000000 { 311 compatible = "qcom,smem"; 312 reg = <0x0 0x46000000 0x0 0x200000>; 313 no-map; 314 315 hwlocks = <&tcsr_mutex 3>; 316 qcom,rpm-msg-ram = <&rpm_msg_ram>; 317 }; 318 319 pil_modem_mem: modem@4ab00000 { 320 reg = <0x0 0x4ab00000 0x0 0x6900000>; 321 no-map; 322 }; 323 324 pil_video_mem: video@51400000 { 325 reg = <0x0 0x51400000 0x0 0x500000>; 326 no-map; 327 }; 328 329 wlan_msa_mem: wlan-msa@51900000 { 330 reg = <0x0 0x51900000 0x0 0x100000>; 331 no-map; 332 }; 333 334 pil_adsp_mem: adsp@51a00000 { 335 reg = <0x0 0x51a00000 0x0 0x1c00000>; 336 no-map; 337 }; 338 339 pil_ipa_fw_mem: ipa-fw@53600000 { 340 reg = <0x0 0x53600000 0x0 0x10000>; 341 no-map; 342 }; 343 344 pil_ipa_gsi_mem: ipa-gsi@53610000 { 345 reg = <0x0 0x53610000 0x0 0x5000>; 346 no-map; 347 }; 348 349 pil_gpu_mem: zap@53615000 { 350 compatible = "shared-dma-pool"; 351 reg = <0x0 0x53615000 0x0 0x2000>; 352 no-map; 353 }; 354 355 cont_splash_memory: framebuffer@5c000000 { 356 reg = <0x0 0x5c000000 0x0 0x00f00000>; 357 no-map; 358 }; 359 360 dfps_data_memory: dpfs-data@5cf00000 { 361 reg = <0x0 0x5cf00000 0x0 0x0100000>; 362 no-map; 363 }; 364 365 removed_mem: reserved@60000000 { 366 reg = <0x0 0x60000000 0x0 0x3900000>; 367 no-map; 368 }; 369 370 rmtfs_mem: memory@89b01000 { 371 compatible = "qcom,rmtfs-mem"; 372 reg = <0x0 0x89b01000 0x0 0x200000>; 373 no-map; 374 375 qcom,client-id = <1>; 376 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 377 }; 378 }; 379 380 smp2p-adsp { 381 compatible = "qcom,smp2p"; 382 qcom,smem = <443>, <429>; 383 384 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 385 386 mboxes = <&apcs_glb 10>; 387 388 qcom,local-pid = <0>; 389 qcom,remote-pid = <2>; 390 391 adsp_smp2p_out: master-kernel { 392 qcom,entry-name = "master-kernel"; 393 #qcom,smem-state-cells = <1>; 394 }; 395 396 adsp_smp2p_in: slave-kernel { 397 qcom,entry-name = "slave-kernel"; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 }; 402 403 smp2p-mpss { 404 compatible = "qcom,smp2p"; 405 qcom,smem = <435>, <428>; 406 407 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 408 409 mboxes = <&apcs_glb 14>; 410 411 qcom,local-pid = <0>; 412 qcom,remote-pid = <1>; 413 414 modem_smp2p_out: master-kernel { 415 qcom,entry-name = "master-kernel"; 416 #qcom,smem-state-cells = <1>; 417 }; 418 419 modem_smp2p_in: slave-kernel { 420 qcom,entry-name = "slave-kernel"; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 }; 424 425 wlan_smp2p_in: wlan-wpss-to-ap { 426 qcom,entry-name = "wlan"; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 }; 431 432 soc: soc@0 { 433 compatible = "simple-bus"; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges = <0 0 0 0 0x10 0>; 437 dma-ranges = <0 0 0 0 0x10 0>; 438 439 tcsr_mutex: hwlock@340000 { 440 compatible = "qcom,tcsr-mutex"; 441 reg = <0x0 0x00340000 0x0 0x20000>; 442 #hwlock-cells = <1>; 443 }; 444 445 tlmm: pinctrl@500000 { 446 compatible = "qcom,qcm2290-tlmm"; 447 reg = <0x0 0x00500000 0x0 0x300000>; 448 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 449 gpio-controller; 450 gpio-ranges = <&tlmm 0 0 127>; 451 wakeup-parent = <&mpm>; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 456 qup_i2c0_default: qup-i2c0-default-state { 457 pins = "gpio0", "gpio1"; 458 function = "qup0"; 459 drive-strength = <2>; 460 bias-pull-up; 461 }; 462 463 qup_i2c1_default: qup-i2c1-default-state { 464 pins = "gpio4", "gpio5"; 465 function = "qup1"; 466 drive-strength = <2>; 467 bias-pull-up; 468 }; 469 470 qup_i2c2_default: qup-i2c2-default-state { 471 pins = "gpio6", "gpio7"; 472 function = "qup2"; 473 drive-strength = <2>; 474 bias-pull-up; 475 }; 476 477 qup_i2c3_default: qup-i2c3-default-state { 478 pins = "gpio8", "gpio9"; 479 function = "qup3"; 480 drive-strength = <2>; 481 bias-pull-up; 482 }; 483 484 qup_i2c4_default: qup-i2c4-default-state { 485 pins = "gpio12", "gpio13"; 486 function = "qup4"; 487 drive-strength = <2>; 488 bias-pull-up; 489 }; 490 491 qup_i2c5_default: qup-i2c5-default-state { 492 pins = "gpio14", "gpio15"; 493 function = "qup5"; 494 drive-strength = <2>; 495 bias-pull-up; 496 }; 497 498 qup_spi0_default: qup-spi0-default-state { 499 pins = "gpio0", "gpio1","gpio2", "gpio3"; 500 function = "qup0"; 501 drive-strength = <2>; 502 bias-pull-up; 503 }; 504 505 qup_spi1_default: qup-spi1-default-state { 506 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 507 function = "qup1"; 508 drive-strength = <2>; 509 bias-pull-up; 510 }; 511 512 qup_spi2_default: qup-spi2-default-state { 513 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 514 function = "qup2"; 515 drive-strength = <2>; 516 bias-pull-up; 517 }; 518 519 qup_spi3_default: qup-spi3-default-state { 520 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 521 function = "qup3"; 522 drive-strength = <2>; 523 bias-pull-up; 524 }; 525 526 qup_spi4_default: qup-spi4-default-state { 527 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 528 function = "qup4"; 529 drive-strength = <2>; 530 bias-pull-up; 531 }; 532 533 qup_spi5_default: qup-spi5-default-state { 534 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 535 function = "qup5"; 536 drive-strength = <2>; 537 bias-pull-up; 538 }; 539 540 qup_uart0_default: qup-uart0-default-state { 541 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 542 function = "qup0"; 543 drive-strength = <2>; 544 bias-disable; 545 }; 546 547 qup_uart4_default: qup-uart4-default-state { 548 pins = "gpio12", "gpio13"; 549 function = "qup4"; 550 drive-strength = <2>; 551 bias-disable; 552 }; 553 554 sdc1_state_on: sdc1-on-state { 555 clk-pins { 556 pins = "sdc1_clk"; 557 drive-strength = <16>; 558 bias-disable; 559 }; 560 561 cmd-pins { 562 pins = "sdc1_cmd"; 563 drive-strength = <10>; 564 bias-pull-up; 565 }; 566 567 data-pins { 568 pins = "sdc1_data"; 569 drive-strength = <10>; 570 bias-pull-up; 571 }; 572 573 rclk-pins { 574 pins = "sdc1_rclk"; 575 bias-pull-down; 576 }; 577 }; 578 579 sdc1_state_off: sdc1-off-state { 580 clk-pins { 581 pins = "sdc1_clk"; 582 drive-strength = <2>; 583 bias-disable; 584 }; 585 586 cmd-pins { 587 pins = "sdc1_cmd"; 588 drive-strength = <2>; 589 bias-pull-up; 590 }; 591 592 data-pins { 593 pins = "sdc1_data"; 594 drive-strength = <2>; 595 bias-pull-up; 596 }; 597 598 rclk-pins { 599 pins = "sdc1_rclk"; 600 bias-pull-down; 601 }; 602 }; 603 604 sdc2_state_on: sdc2-on-state { 605 clk-pins { 606 pins = "sdc2_clk"; 607 drive-strength = <16>; 608 bias-disable; 609 }; 610 611 cmd-pins { 612 pins = "sdc2_cmd"; 613 drive-strength = <10>; 614 bias-pull-up; 615 }; 616 617 data-pins { 618 pins = "sdc2_data"; 619 drive-strength = <10>; 620 bias-pull-up; 621 }; 622 }; 623 624 sdc2_state_off: sdc2-off-state { 625 clk-pins { 626 pins = "sdc2_clk"; 627 drive-strength = <2>; 628 bias-disable; 629 }; 630 631 cmd-pins { 632 pins = "sdc2_cmd"; 633 drive-strength = <2>; 634 bias-pull-up; 635 }; 636 637 data-pins { 638 pins = "sdc2_data"; 639 drive-strength = <2>; 640 bias-pull-up; 641 }; 642 }; 643 }; 644 645 gcc: clock-controller@1400000 { 646 compatible = "qcom,gcc-qcm2290"; 647 reg = <0x0 0x01400000 0x0 0x1f0000>; 648 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 649 clock-names = "bi_tcxo", "sleep_clk"; 650 #clock-cells = <1>; 651 #reset-cells = <1>; 652 #power-domain-cells = <1>; 653 }; 654 655 usb_hsphy: phy@1613000 { 656 compatible = "qcom,qcm2290-qusb2-phy"; 657 reg = <0x0 0x01613000 0x0 0x180>; 658 659 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 660 <&rpmcc RPM_SMD_XO_CLK_SRC>; 661 clock-names = "cfg_ahb", "ref"; 662 663 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 664 nvmem-cells = <&qusb2_hstx_trim>; 665 #phy-cells = <0>; 666 667 status = "disabled"; 668 }; 669 670 usb_qmpphy: phy@1615000 { 671 compatible = "qcom,qcm2290-qmp-usb3-phy"; 672 reg = <0x0 0x01615000 0x0 0x1000>; 673 674 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 675 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 676 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 677 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 678 clock-names = "cfg_ahb", 679 "ref", 680 "com_aux", 681 "pipe"; 682 683 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 684 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 685 reset-names = "phy", 686 "phy_phy"; 687 688 #clock-cells = <0>; 689 clock-output-names = "usb3_phy_pipe_clk_src"; 690 691 #phy-cells = <0>; 692 693 status = "disabled"; 694 }; 695 696 system_noc: interconnect@1880000 { 697 compatible = "qcom,qcm2290-snoc"; 698 reg = <0x0 0x01880000 0x0 0x60200>; 699 #interconnect-cells = <2>; 700 701 qup_virt: interconnect-qup { 702 compatible = "qcom,qcm2290-qup-virt"; 703 #interconnect-cells = <2>; 704 }; 705 706 mmnrt_virt: interconnect-mmnrt { 707 compatible = "qcom,qcm2290-mmnrt-virt"; 708 #interconnect-cells = <2>; 709 }; 710 711 mmrt_virt: interconnect-mmrt { 712 compatible = "qcom,qcm2290-mmrt-virt"; 713 #interconnect-cells = <2>; 714 }; 715 }; 716 717 config_noc: interconnect@1900000 { 718 compatible = "qcom,qcm2290-cnoc"; 719 reg = <0x0 0x01900000 0x0 0x8200>; 720 #interconnect-cells = <2>; 721 }; 722 723 qfprom@1b44000 { 724 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 725 reg = <0x0 0x01b44000 0x0 0x3000>; 726 #address-cells = <1>; 727 #size-cells = <1>; 728 729 qusb2_hstx_trim: hstx-trim@25b { 730 reg = <0x25b 0x1>; 731 bits = <1 4>; 732 }; 733 }; 734 735 pmu@1b8e300 { 736 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 737 reg = <0x0 0x01b8e300 0x0 0x600>; 738 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 739 740 operating-points-v2 = <&cpu_bwmon_opp_table>; 741 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 742 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 743 744 cpu_bwmon_opp_table: opp-table { 745 compatible = "operating-points-v2"; 746 747 opp-0 { 748 opp-peak-kBps = <(200 * 4 * 1000)>; 749 }; 750 751 opp-1 { 752 opp-peak-kBps = <(300 * 4 * 1000)>; 753 }; 754 755 opp-2 { 756 opp-peak-kBps = <(451 * 4 * 1000)>; 757 }; 758 759 opp-3 { 760 opp-peak-kBps = <(547 * 4 * 1000)>; 761 }; 762 763 opp-4 { 764 opp-peak-kBps = <(681 * 4 * 1000)>; 765 }; 766 767 opp-5 { 768 opp-peak-kBps = <(768 * 4 * 1000)>; 769 }; 770 771 opp-6 { 772 opp-peak-kBps = <(1017 * 4 * 1000)>; 773 }; 774 775 opp-7 { 776 opp-peak-kBps = <(1353 * 4 * 1000)>; 777 }; 778 779 opp-8 { 780 opp-peak-kBps = <(1555 * 4 * 1000)>; 781 }; 782 783 opp-9 { 784 opp-peak-kBps = <(1804 * 4 * 1000)>; 785 }; 786 }; 787 }; 788 789 spmi_bus: spmi@1c40000 { 790 compatible = "qcom,spmi-pmic-arb"; 791 reg = <0x0 0x01c40000 0x0 0x1100>, 792 <0x0 0x01e00000 0x0 0x2000000>, 793 <0x0 0x03e00000 0x0 0x100000>, 794 <0x0 0x03f00000 0x0 0xa0000>, 795 <0x0 0x01c0a000 0x0 0x26000>; 796 reg-names = "core", 797 "chnls", 798 "obsrvr", 799 "intr", 800 "cnfg"; 801 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-names = "periph_irq"; 803 qcom,ee = <0>; 804 qcom,channel = <0>; 805 #address-cells = <2>; 806 #size-cells = <0>; 807 interrupt-controller; 808 #interrupt-cells = <4>; 809 }; 810 811 tsens0: thermal-sensor@4411000 { 812 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 813 reg = <0x0 0x04411000 0x0 0x1ff>, 814 <0x0 0x04410000 0x0 0x8>; 815 #qcom,sensors = <10>; 816 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 817 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 818 interrupt-names = "uplow", "critical"; 819 #thermal-sensor-cells = <1>; 820 }; 821 822 rng: rng@4453000 { 823 compatible = "qcom,prng-ee"; 824 reg = <0x0 0x04453000 0x0 0x1000>; 825 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 826 clock-names = "core"; 827 }; 828 829 bimc: interconnect@4480000 { 830 compatible = "qcom,qcm2290-bimc"; 831 reg = <0x0 0x04480000 0x0 0x80000>; 832 #interconnect-cells = <2>; 833 }; 834 835 rpm_msg_ram: sram@45f0000 { 836 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 837 reg = <0x0 0x045f0000 0x0 0x7000>; 838 #address-cells = <1>; 839 #size-cells = <1>; 840 ranges = <0 0x0 0x045f0000 0x7000>; 841 842 apss_mpm: sram@1b8 { 843 reg = <0x1b8 0x48>; 844 }; 845 }; 846 847 sram@4690000 { 848 compatible = "qcom,rpm-stats"; 849 reg = <0x0 0x04690000 0x0 0x10000>; 850 }; 851 852 sdhc_1: mmc@4744000 { 853 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 854 reg = <0x0 0x04744000 0x0 0x1000>, 855 <0x0 0x04745000 0x0 0x1000>, 856 <0x0 0x04748000 0x0 0x8000>; 857 reg-names = "hc", 858 "cqhci", 859 "ice"; 860 861 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "hc_irq", "pwr_irq"; 864 865 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 866 <&gcc GCC_SDCC1_APPS_CLK>, 867 <&rpmcc RPM_SMD_XO_CLK_SRC>, 868 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 869 clock-names = "iface", 870 "core", 871 "xo", 872 "ice"; 873 874 resets = <&gcc GCC_SDCC1_BCR>; 875 876 power-domains = <&rpmpd QCM2290_VDDCX>; 877 operating-points-v2 = <&sdhc1_opp_table>; 878 iommus = <&apps_smmu 0xc0 0x0>; 879 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 880 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 881 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 882 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 883 interconnect-names = "sdhc-ddr", 884 "cpu-sdhc"; 885 886 qcom,dll-config = <0x000f642c>; 887 qcom,ddr-config = <0x80040868>; 888 bus-width = <8>; 889 890 status = "disabled"; 891 892 sdhc1_opp_table: opp-table { 893 compatible = "operating-points-v2"; 894 895 opp-100000000 { 896 opp-hz = /bits/ 64 <100000000>; 897 required-opps = <&rpmpd_opp_low_svs>; 898 opp-peak-kBps = <250000 133320>; 899 opp-avg-kBps = <102400 65000>; 900 }; 901 902 opp-192000000 { 903 opp-hz = /bits/ 64 <192000000>; 904 required-opps = <&rpmpd_opp_low_svs>; 905 opp-peak-kBps = <800000 300000>; 906 opp-avg-kBps = <204800 200000>; 907 }; 908 909 opp-384000000 { 910 opp-hz = /bits/ 64 <384000000>; 911 required-opps = <&rpmpd_opp_svs_plus>; 912 opp-peak-kBps = <800000 300000>; 913 opp-avg-kBps = <204800 200000>; 914 }; 915 }; 916 }; 917 918 sdhc_2: mmc@4784000 { 919 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 920 reg = <0x0 0x04784000 0x0 0x1000>; 921 reg-names = "hc"; 922 923 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "hc_irq", "pwr_irq"; 926 927 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 928 <&gcc GCC_SDCC2_APPS_CLK>, 929 <&rpmcc RPM_SMD_XO_CLK_SRC>; 930 clock-names = "iface", 931 "core", 932 "xo"; 933 934 resets = <&gcc GCC_SDCC2_BCR>; 935 936 power-domains = <&rpmpd QCM2290_VDDCX>; 937 operating-points-v2 = <&sdhc2_opp_table>; 938 iommus = <&apps_smmu 0xa0 0x0>; 939 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 940 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 941 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 942 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 943 interconnect-names = "sdhc-ddr", 944 "cpu-sdhc"; 945 946 qcom,dll-config = <0x0007642c>; 947 qcom,ddr-config = <0x80040868>; 948 bus-width = <4>; 949 950 status = "disabled"; 951 952 sdhc2_opp_table: opp-table { 953 compatible = "operating-points-v2"; 954 955 opp-100000000 { 956 opp-hz = /bits/ 64 <100000000>; 957 required-opps = <&rpmpd_opp_low_svs>; 958 opp-peak-kBps = <250000 133320>; 959 opp-avg-kBps = <261438 150000>; 960 }; 961 962 opp-202000000 { 963 opp-hz = /bits/ 64 <202000000>; 964 required-opps = <&rpmpd_opp_svs_plus>; 965 opp-peak-kBps = <800000 300000>; 966 opp-avg-kBps = <261438 300000>; 967 }; 968 }; 969 }; 970 971 gpi_dma0: dma-controller@4a00000 { 972 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 973 reg = <0x0 0x04a00000 0x0 0x60000>; 974 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 984 dma-channels = <10>; 985 dma-channel-mask = <0x1f>; 986 iommus = <&apps_smmu 0xf6 0x0>; 987 #dma-cells = <3>; 988 status = "disabled"; 989 }; 990 991 qupv3_id_0: geniqup@4ac0000 { 992 compatible = "qcom,geni-se-qup"; 993 reg = <0x0 0x04ac0000 0x0 0x2000>; 994 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 995 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 996 clock-names = "m-ahb", "s-ahb"; 997 iommus = <&apps_smmu 0xe3 0x0>; 998 #address-cells = <2>; 999 #size-cells = <2>; 1000 ranges; 1001 status = "disabled"; 1002 1003 i2c0: i2c@4a80000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0x0 0x04a80000 0x0 0x4000>; 1006 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1008 clock-names = "se"; 1009 pinctrl-0 = <&qup_i2c0_default>; 1010 pinctrl-names = "default"; 1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1015 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1016 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1017 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1018 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1019 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1020 interconnect-names = "qup-core", 1021 "qup-config", 1022 "qup-memory"; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 status = "disabled"; 1026 }; 1027 1028 spi0: spi@4a80000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0x0 0x04a80000 0x0 0x4000>; 1031 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1033 clock-names = "se"; 1034 pinctrl-0 = <&qup_spi0_default>; 1035 pinctrl-names = "default"; 1036 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1037 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1038 dma-names = "tx", "rx"; 1039 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1040 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1041 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1042 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1043 interconnect-names = "qup-core", 1044 "qup-config"; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 uart0: serial@4a80000 { 1051 compatible = "qcom,geni-uart"; 1052 reg = <0x0 0x04a80000 0x0 0x4000>; 1053 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1055 clock-names = "se"; 1056 pinctrl-0 = <&qup_uart0_default>; 1057 pinctrl-names = "default"; 1058 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1059 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1060 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1061 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1062 interconnect-names = "qup-core", 1063 "qup-config"; 1064 status = "disabled"; 1065 }; 1066 1067 i2c1: i2c@4a84000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0x0 0x04a84000 0x0 0x4000>; 1070 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1072 clock-names = "se"; 1073 pinctrl-0 = <&qup_i2c1_default>; 1074 pinctrl-names = "default"; 1075 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1076 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1077 dma-names = "tx", "rx"; 1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1079 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1080 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1081 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1082 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1083 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1084 interconnect-names = "qup-core", 1085 "qup-config", 1086 "qup-memory"; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 spi1: spi@4a84000 { 1093 compatible = "qcom,geni-spi"; 1094 reg = <0x0 0x04a84000 0x0 0x4000>; 1095 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1097 clock-names = "se"; 1098 pinctrl-0 = <&qup_spi1_default>; 1099 pinctrl-names = "default"; 1100 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1101 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1102 dma-names = "tx", "rx"; 1103 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1104 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1105 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1106 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1107 interconnect-names = "qup-core", 1108 "qup-config"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c2: i2c@4a88000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0x0 0x04a88000 0x0 0x4000>; 1117 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1119 clock-names = "se"; 1120 pinctrl-0 = <&qup_i2c2_default>; 1121 pinctrl-names = "default"; 1122 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1123 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1124 dma-names = "tx", "rx"; 1125 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1126 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1127 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1128 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1129 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1130 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1131 interconnect-names = "qup-core", 1132 "qup-config", 1133 "qup-memory"; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 spi2: spi@4a88000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0x0 0x04a88000 0x0 0x4000>; 1142 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1144 clock-names = "se"; 1145 pinctrl-0 = <&qup_spi2_default>; 1146 pinctrl-names = "default"; 1147 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1148 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1149 dma-names = "tx", "rx"; 1150 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1151 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1152 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1153 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1154 interconnect-names = "qup-core", 1155 "qup-config"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c3: i2c@4a8c000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0x0 0x04a8c000 0x0 0x4000>; 1164 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1166 clock-names = "se"; 1167 pinctrl-0 = <&qup_i2c3_default>; 1168 pinctrl-names = "default"; 1169 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1170 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1171 dma-names = "tx", "rx"; 1172 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1173 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1174 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1175 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1176 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1177 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1178 interconnect-names = "qup-core", 1179 "qup-config", 1180 "qup-memory"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 status = "disabled"; 1184 }; 1185 1186 spi3: spi@4a8c000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0x0 0x04a8c000 0x0 0x4000>; 1189 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1191 clock-names = "se"; 1192 pinctrl-0 = <&qup_spi3_default>; 1193 pinctrl-names = "default"; 1194 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1195 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1196 dma-names = "tx", "rx"; 1197 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1198 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1199 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1200 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1201 interconnect-names = "qup-core", 1202 "qup-config"; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 i2c4: i2c@4a90000 { 1209 compatible = "qcom,geni-i2c"; 1210 reg = <0x0 0x04a90000 0x0 0x4000>; 1211 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1213 clock-names = "se"; 1214 pinctrl-0 = <&qup_i2c4_default>; 1215 pinctrl-names = "default"; 1216 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1217 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1218 dma-names = "tx", "rx"; 1219 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1220 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1221 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1222 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1223 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1224 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1225 interconnect-names = "qup-core", 1226 "qup-config", 1227 "qup-memory"; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 1233 spi4: spi@4a90000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0x0 0x04a90000 0x0 0x4000>; 1236 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_spi4_default>; 1241 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1242 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1243 dma-names = "tx", "rx"; 1244 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1245 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1246 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1247 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1248 interconnect-names = "qup-core", 1249 "qup-config"; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 uart4: serial@4a90000 { 1256 compatible = "qcom,geni-uart"; 1257 reg = <0x0 0x04a90000 0x0 0x4000>; 1258 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1260 clock-names = "se"; 1261 pinctrl-0 = <&qup_uart4_default>; 1262 pinctrl-names = "default"; 1263 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1264 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1265 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1266 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1267 interconnect-names = "qup-core", 1268 "qup-config"; 1269 status = "disabled"; 1270 }; 1271 1272 i2c5: i2c@4a94000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0x0 0x04a94000 0x0 0x4000>; 1275 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1277 clock-names = "se"; 1278 pinctrl-0 = <&qup_i2c5_default>; 1279 pinctrl-names = "default"; 1280 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1281 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1282 dma-names = "tx", "rx"; 1283 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1284 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1285 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1286 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1287 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1288 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1289 interconnect-names = "qup-core", 1290 "qup-config", 1291 "qup-memory"; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 status = "disabled"; 1295 }; 1296 1297 spi5: spi@4a94000 { 1298 compatible = "qcom,geni-spi"; 1299 reg = <0x0 0x04a94000 0x0 0x4000>; 1300 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1302 clock-names = "se"; 1303 pinctrl-0 = <&qup_spi5_default>; 1304 pinctrl-names = "default"; 1305 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1306 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1307 dma-names = "tx", "rx"; 1308 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1309 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1310 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1311 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1312 interconnect-names = "qup-core", 1313 "qup-config"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 }; 1319 1320 usb: usb@4ef8800 { 1321 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1322 reg = <0x0 0x04ef8800 0x0 0x400>; 1323 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1324 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1325 interrupt-names = "hs_phy_irq", 1326 "ss_phy_irq"; 1327 1328 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1329 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1330 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1331 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1332 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1333 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1334 clock-names = "cfg_noc", 1335 "core", 1336 "iface", 1337 "sleep", 1338 "mock_utmi", 1339 "xo"; 1340 1341 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1342 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1343 assigned-clock-rates = <19200000>, <133333333>; 1344 1345 resets = <&gcc GCC_USB30_PRIM_BCR>; 1346 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1347 /* TODO: USB<->IPA path */ 1348 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1349 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1350 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1351 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1352 interconnect-names = "usb-ddr", 1353 "apps-usb"; 1354 wakeup-source; 1355 1356 #address-cells = <2>; 1357 #size-cells = <2>; 1358 ranges; 1359 1360 status = "disabled"; 1361 1362 usb_dwc3: usb@4e00000 { 1363 compatible = "snps,dwc3"; 1364 reg = <0x0 0x04e00000 0x0 0xcd00>; 1365 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1366 phys = <&usb_hsphy>, <&usb_qmpphy>; 1367 phy-names = "usb2-phy", "usb3-phy"; 1368 iommus = <&apps_smmu 0x120 0x0>; 1369 snps,dis_u2_susphy_quirk; 1370 snps,dis_enblslpm_quirk; 1371 snps,has-lpm-erratum; 1372 snps,hird-threshold = /bits/ 8 <0x10>; 1373 snps,usb3_lpm_capable; 1374 maximum-speed = "super-speed"; 1375 dr_mode = "otg"; 1376 }; 1377 }; 1378 1379 mdss: display-subsystem@5e00000 { 1380 compatible = "qcom,qcm2290-mdss"; 1381 reg = <0x0 0x05e00000 0x0 0x1000>; 1382 reg-names = "mdss"; 1383 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1384 interrupt-controller; 1385 #interrupt-cells = <1>; 1386 1387 clocks = <&gcc GCC_DISP_AHB_CLK>, 1388 <&gcc GCC_DISP_HF_AXI_CLK>, 1389 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1390 clock-names = "iface", 1391 "bus", 1392 "core"; 1393 1394 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1395 1396 power-domains = <&dispcc MDSS_GDSC>; 1397 1398 iommus = <&apps_smmu 0x420 0x2>, 1399 <&apps_smmu 0x421 0x0>; 1400 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1401 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1402 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1403 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1404 interconnect-names = "mdp0-mem", 1405 "cpu-cfg"; 1406 1407 #address-cells = <2>; 1408 #size-cells = <2>; 1409 ranges; 1410 1411 status = "disabled"; 1412 1413 mdp: display-controller@5e01000 { 1414 compatible = "qcom,qcm2290-dpu"; 1415 reg = <0x0 0x05e01000 0x0 0x8f000>, 1416 <0x0 0x05eb0000 0x0 0x2008>; 1417 reg-names = "mdp", 1418 "vbif"; 1419 1420 interrupt-parent = <&mdss>; 1421 interrupts = <0>; 1422 1423 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1424 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1425 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1426 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1427 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1428 clock-names = "bus", 1429 "iface", 1430 "core", 1431 "lut", 1432 "vsync"; 1433 1434 operating-points-v2 = <&mdp_opp_table>; 1435 power-domains = <&rpmpd QCM2290_VDDCX>; 1436 1437 ports { 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 1441 port@0 { 1442 reg = <0>; 1443 dpu_intf1_out: endpoint { 1444 remote-endpoint = <&mdss_dsi0_in>; 1445 }; 1446 }; 1447 }; 1448 1449 mdp_opp_table: opp-table { 1450 compatible = "operating-points-v2"; 1451 1452 opp-19200000 { 1453 opp-hz = /bits/ 64 <19200000>; 1454 required-opps = <&rpmpd_opp_min_svs>; 1455 }; 1456 1457 opp-192000000 { 1458 opp-hz = /bits/ 64 <192000000>; 1459 required-opps = <&rpmpd_opp_low_svs>; 1460 }; 1461 1462 opp-256000000 { 1463 opp-hz = /bits/ 64 <256000000>; 1464 required-opps = <&rpmpd_opp_svs>; 1465 }; 1466 1467 opp-307200000 { 1468 opp-hz = /bits/ 64 <307200000>; 1469 required-opps = <&rpmpd_opp_svs_plus>; 1470 }; 1471 1472 opp-384000000 { 1473 opp-hz = /bits/ 64 <384000000>; 1474 required-opps = <&rpmpd_opp_nom>; 1475 }; 1476 }; 1477 }; 1478 1479 mdss_dsi0: dsi@5e94000 { 1480 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1481 reg = <0x0 0x05e94000 0x0 0x400>; 1482 reg-names = "dsi_ctrl"; 1483 1484 interrupt-parent = <&mdss>; 1485 interrupts = <4>; 1486 1487 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1488 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1489 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1490 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1491 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1492 <&gcc GCC_DISP_HF_AXI_CLK>; 1493 clock-names = "byte", 1494 "byte_intf", 1495 "pixel", 1496 "core", 1497 "iface", 1498 "bus"; 1499 1500 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1501 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1502 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1503 <&mdss_dsi0_phy 1>; 1504 1505 operating-points-v2 = <&dsi_opp_table>; 1506 power-domains = <&rpmpd QCM2290_VDDCX>; 1507 phys = <&mdss_dsi0_phy>; 1508 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 1512 status = "disabled"; 1513 1514 dsi_opp_table: opp-table { 1515 compatible = "operating-points-v2"; 1516 1517 opp-19200000 { 1518 opp-hz = /bits/ 64 <19200000>; 1519 required-opps = <&rpmpd_opp_min_svs>; 1520 }; 1521 1522 opp-164000000 { 1523 opp-hz = /bits/ 64 <164000000>; 1524 required-opps = <&rpmpd_opp_low_svs>; 1525 }; 1526 1527 opp-187500000 { 1528 opp-hz = /bits/ 64 <187500000>; 1529 required-opps = <&rpmpd_opp_svs>; 1530 }; 1531 }; 1532 1533 ports { 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 1537 port@0 { 1538 reg = <0>; 1539 1540 mdss_dsi0_in: endpoint { 1541 remote-endpoint = <&dpu_intf1_out>; 1542 }; 1543 }; 1544 1545 port@1 { 1546 reg = <1>; 1547 1548 mdss_dsi0_out: endpoint { 1549 }; 1550 }; 1551 }; 1552 }; 1553 1554 mdss_dsi0_phy: phy@5e94400 { 1555 compatible = "qcom,dsi-phy-14nm-2290"; 1556 reg = <0x0 0x05e94400 0x0 0x100>, 1557 <0x0 0x05e94500 0x0 0x300>, 1558 <0x0 0x05e94800 0x0 0x188>; 1559 reg-names = "dsi_phy", 1560 "dsi_phy_lane", 1561 "dsi_pll"; 1562 1563 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1564 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1565 clock-names = "iface", 1566 "ref"; 1567 1568 power-domains = <&rpmpd QCM2290_VDDMX>; 1569 required-opps = <&rpmpd_opp_nom>; 1570 1571 #clock-cells = <1>; 1572 #phy-cells = <0>; 1573 1574 status = "disabled"; 1575 }; 1576 }; 1577 1578 dispcc: clock-controller@5f00000 { 1579 compatible = "qcom,qcm2290-dispcc"; 1580 reg = <0x0 0x05f00000 0x0 0x20000>; 1581 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1582 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 1583 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1584 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1585 <&mdss_dsi0_phy 0>, 1586 <&mdss_dsi0_phy 1>; 1587 clock-names = "bi_tcxo", 1588 "bi_tcxo_ao", 1589 "gcc_disp_gpll0_clk_src", 1590 "gcc_disp_gpll0_div_clk_src", 1591 "dsi0_phy_pll_out_byteclk", 1592 "dsi0_phy_pll_out_dsiclk"; 1593 #power-domain-cells = <1>; 1594 #clock-cells = <1>; 1595 #reset-cells = <1>; 1596 }; 1597 1598 remoteproc_mpss: remoteproc@6080000 { 1599 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1600 reg = <0x0 0x06080000 0x0 0x100>; 1601 1602 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1603 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1604 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1605 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1606 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1607 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1608 interrupt-names = "wdog", 1609 "fatal", 1610 "ready", 1611 "handover", 1612 "stop-ack", 1613 "shutdown-ack"; 1614 1615 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1616 clock-names = "xo"; 1617 1618 power-domains = <&rpmpd QCM2290_VDDCX>; 1619 1620 memory-region = <&pil_modem_mem>; 1621 1622 qcom,smem-states = <&modem_smp2p_out 0>; 1623 qcom,smem-state-names = "stop"; 1624 1625 status = "disabled"; 1626 1627 glink-edge { 1628 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1629 label = "mpss"; 1630 qcom,remote-pid = <1>; 1631 mboxes = <&apcs_glb 12>; 1632 }; 1633 }; 1634 1635 remoteproc_adsp: remoteproc@ab00000 { 1636 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1637 reg = <0x0 0x0ab00000 0x0 0x100>; 1638 1639 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1640 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1641 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1642 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1643 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1644 interrupt-names = "wdog", 1645 "fatal", 1646 "ready", 1647 "handover", 1648 "stop-ack"; 1649 1650 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1651 clock-names = "xo"; 1652 1653 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1654 <&rpmpd QCM2290_VDD_LPI_MX>; 1655 1656 memory-region = <&pil_adsp_mem>; 1657 1658 qcom,smem-states = <&adsp_smp2p_out 0>; 1659 qcom,smem-state-names = "stop"; 1660 1661 status = "disabled"; 1662 1663 glink-edge { 1664 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1665 label = "lpass"; 1666 qcom,remote-pid = <2>; 1667 mboxes = <&apcs_glb 8>; 1668 }; 1669 }; 1670 1671 apps_smmu: iommu@c600000 { 1672 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1673 reg = <0x0 0x0c600000 0x0 0x80000>; 1674 #iommu-cells = <2>; 1675 #global-interrupts = <1>; 1676 1677 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1742 }; 1743 1744 wifi: wifi@c800000 { 1745 compatible = "qcom,wcn3990-wifi"; 1746 reg = <0x0 0x0c800000 0x0 0x800000>; 1747 reg-names = "membase"; 1748 memory-region = <&wlan_msa_mem>; 1749 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1761 iommus = <&apps_smmu 0x1a0 0x1>; 1762 qcom,msa-fixed-perm; 1763 status = "disabled"; 1764 }; 1765 1766 watchdog@f017000 { 1767 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1768 reg = <0x0 0x0f017000 0x0 0x1000>; 1769 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1770 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1771 clocks = <&sleep_clk>; 1772 }; 1773 1774 apcs_glb: mailbox@f111000 { 1775 compatible = "qcom,qcm2290-apcs-hmss-global"; 1776 reg = <0x0 0x0f111000 0x0 0x1000>; 1777 #mbox-cells = <1>; 1778 }; 1779 1780 timer@f120000 { 1781 compatible = "arm,armv7-timer-mem"; 1782 reg = <0x0 0x0f120000 0x0 0x1000>; 1783 #address-cells = <1>; 1784 #size-cells = <1>; 1785 ranges = <0 0x0 0x0f121000 0x8000>; 1786 1787 frame@0 { 1788 reg = <0x0 0x1000>, 1789 <0x1000 0x1000>; 1790 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1792 frame-number = <0>; 1793 }; 1794 1795 frame@2000 { 1796 reg = <0x2000 0x1000>; 1797 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1798 frame-number = <1>; 1799 status = "disabled"; 1800 }; 1801 1802 frame@3000 { 1803 reg = <0x3000 0x1000>; 1804 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1805 frame-number = <2>; 1806 status = "disabled"; 1807 }; 1808 1809 frame@4000 { 1810 reg = <0x4000 0x1000>; 1811 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1812 frame-number = <3>; 1813 status = "disabled"; 1814 }; 1815 1816 frame@5000 { 1817 reg = <0x5000 0x1000>; 1818 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1819 frame-number = <4>; 1820 status = "disabled"; 1821 }; 1822 1823 frame@6000 { 1824 reg = <0x6000 0x1000>; 1825 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1826 frame-number = <5>; 1827 status = "disabled"; 1828 }; 1829 1830 frame@7000 { 1831 reg = <0x7000 0x1000>; 1832 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1833 frame-number = <6>; 1834 status = "disabled"; 1835 }; 1836 }; 1837 1838 intc: interrupt-controller@f200000 { 1839 compatible = "arm,gic-v3"; 1840 reg = <0x0 0x0f200000 0x0 0x10000>, 1841 <0x0 0x0f300000 0x0 0x100000>; 1842 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1843 #interrupt-cells = <3>; 1844 interrupt-controller; 1845 interrupt-parent = <&intc>; 1846 #redistributor-regions = <1>; 1847 redistributor-stride = <0x0 0x20000>; 1848 }; 1849 1850 cpufreq_hw: cpufreq@f521000 { 1851 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 1852 reg = <0x0 0x0f521000 0x0 0x1000>; 1853 reg-names = "freq-domain0"; 1854 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1855 interrupt-names = "dcvsh-irq-0"; 1856 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1857 clock-names = "xo", "alternate"; 1858 1859 #freq-domain-cells = <1>; 1860 #clock-cells = <1>; 1861 }; 1862 }; 1863 1864 thermal-zones { 1865 mapss-thermal { 1866 polling-delay-passive = <0>; 1867 polling-delay = <0>; 1868 1869 thermal-sensors = <&tsens0 0>; 1870 1871 trips { 1872 mapss_alert0: trip-point0 { 1873 temperature = <90000>; 1874 hysteresis = <2000>; 1875 type = "passive"; 1876 }; 1877 1878 mapss_alert1: trip-point1 { 1879 temperature = <95000>; 1880 hysteresis = <2000>; 1881 type = "passive"; 1882 }; 1883 1884 mapss_crit: mapss-crit { 1885 temperature = <110000>; 1886 hysteresis = <1000>; 1887 type = "critical"; 1888 }; 1889 }; 1890 }; 1891 1892 video-thermal { 1893 polling-delay-passive = <0>; 1894 polling-delay = <0>; 1895 1896 thermal-sensors = <&tsens0 1>; 1897 1898 trips { 1899 video_alert0: trip-point0 { 1900 temperature = <90000>; 1901 hysteresis = <2000>; 1902 type = "passive"; 1903 }; 1904 1905 video_alert1: trip-point1 { 1906 temperature = <95000>; 1907 hysteresis = <2000>; 1908 type = "passive"; 1909 }; 1910 1911 video_crit: video-crit { 1912 temperature = <110000>; 1913 hysteresis = <1000>; 1914 type = "critical"; 1915 }; 1916 }; 1917 }; 1918 1919 wlan-thermal { 1920 polling-delay-passive = <0>; 1921 polling-delay = <0>; 1922 1923 thermal-sensors = <&tsens0 2>; 1924 1925 trips { 1926 wlan_alert0: trip-point0 { 1927 temperature = <90000>; 1928 hysteresis = <2000>; 1929 type = "passive"; 1930 }; 1931 1932 wlan_alert1: trip-point1 { 1933 temperature = <95000>; 1934 hysteresis = <2000>; 1935 type = "passive"; 1936 }; 1937 1938 wlan_crit: wlan-crit { 1939 temperature = <110000>; 1940 hysteresis = <1000>; 1941 type = "critical"; 1942 }; 1943 }; 1944 }; 1945 1946 cpuss0-thermal { 1947 polling-delay-passive = <0>; 1948 polling-delay = <0>; 1949 1950 thermal-sensors = <&tsens0 3>; 1951 1952 trips { 1953 cpuss0_alert0: trip-point0 { 1954 temperature = <90000>; 1955 hysteresis = <2000>; 1956 type = "passive"; 1957 }; 1958 1959 cpuss0_alert1: trip-point1 { 1960 temperature = <95000>; 1961 hysteresis = <2000>; 1962 type = "passive"; 1963 }; 1964 1965 cpuss0_crit: cpuss0-crit { 1966 temperature = <110000>; 1967 hysteresis = <1000>; 1968 type = "critical"; 1969 }; 1970 }; 1971 }; 1972 1973 cpuss1-thermal { 1974 polling-delay-passive = <0>; 1975 polling-delay = <0>; 1976 1977 thermal-sensors = <&tsens0 4>; 1978 1979 trips { 1980 cpuss1_alert0: trip-point0 { 1981 temperature = <90000>; 1982 hysteresis = <2000>; 1983 type = "passive"; 1984 }; 1985 1986 cpuss1_alert1: trip-point1 { 1987 temperature = <95000>; 1988 hysteresis = <2000>; 1989 type = "passive"; 1990 }; 1991 1992 cpuss1_crit: cpuss1-crit { 1993 temperature = <110000>; 1994 hysteresis = <1000>; 1995 type = "critical"; 1996 }; 1997 }; 1998 }; 1999 2000 mdm0-thermal { 2001 polling-delay-passive = <0>; 2002 polling-delay = <0>; 2003 2004 thermal-sensors = <&tsens0 5>; 2005 2006 trips { 2007 mdm0_alert0: trip-point0 { 2008 temperature = <90000>; 2009 hysteresis = <2000>; 2010 type = "passive"; 2011 }; 2012 2013 mdm0_alert1: trip-point1 { 2014 temperature = <95000>; 2015 hysteresis = <2000>; 2016 type = "passive"; 2017 }; 2018 2019 mdm0_crit: mdm0-crit { 2020 temperature = <110000>; 2021 hysteresis = <1000>; 2022 type = "critical"; 2023 }; 2024 }; 2025 }; 2026 2027 mdm1-thermal { 2028 polling-delay-passive = <0>; 2029 polling-delay = <0>; 2030 2031 thermal-sensors = <&tsens0 6>; 2032 2033 trips { 2034 mdm1_alert0: trip-point0 { 2035 temperature = <90000>; 2036 hysteresis = <2000>; 2037 type = "passive"; 2038 }; 2039 2040 mdm1_alert1: trip-point1 { 2041 temperature = <95000>; 2042 hysteresis = <2000>; 2043 type = "passive"; 2044 }; 2045 2046 mdm1_crit: mdm1-crit { 2047 temperature = <110000>; 2048 hysteresis = <1000>; 2049 type = "critical"; 2050 }; 2051 }; 2052 }; 2053 2054 gpu-thermal { 2055 polling-delay-passive = <0>; 2056 polling-delay = <0>; 2057 2058 thermal-sensors = <&tsens0 7>; 2059 2060 trips { 2061 gpu_alert0: trip-point0 { 2062 temperature = <90000>; 2063 hysteresis = <2000>; 2064 type = "passive"; 2065 }; 2066 2067 gpu_alert1: trip-point1 { 2068 temperature = <95000>; 2069 hysteresis = <2000>; 2070 type = "passive"; 2071 }; 2072 2073 gpu_crit: gpu-crit { 2074 temperature = <110000>; 2075 hysteresis = <1000>; 2076 type = "critical"; 2077 }; 2078 }; 2079 }; 2080 2081 hm-center-thermal { 2082 polling-delay-passive = <0>; 2083 polling-delay = <0>; 2084 2085 thermal-sensors = <&tsens0 8>; 2086 2087 trips { 2088 hm_center_alert0: trip-point0 { 2089 temperature = <90000>; 2090 hysteresis = <2000>; 2091 type = "passive"; 2092 }; 2093 2094 hm_center_alert1: trip-point1 { 2095 temperature = <95000>; 2096 hysteresis = <2000>; 2097 type = "passive"; 2098 }; 2099 2100 hm_center_crit: hm-center-crit { 2101 temperature = <110000>; 2102 hysteresis = <1000>; 2103 type = "critical"; 2104 }; 2105 }; 2106 }; 2107 2108 camera-thermal { 2109 polling-delay-passive = <0>; 2110 polling-delay = <0>; 2111 2112 thermal-sensors = <&tsens0 9>; 2113 2114 trips { 2115 camera_alert0: trip-point0 { 2116 temperature = <90000>; 2117 hysteresis = <2000>; 2118 type = "passive"; 2119 }; 2120 2121 camera_alert1: trip-point1 { 2122 temperature = <95000>; 2123 hysteresis = <2000>; 2124 type = "passive"; 2125 }; 2126 2127 camera_crit: camera-crit { 2128 temperature = <110000>; 2129 hysteresis = <1000>; 2130 type = "critical"; 2131 }; 2132 }; 2133 }; 2134 }; 2135 2136 timer { 2137 compatible = "arm,armv8-timer"; 2138 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2139 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2140 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2141 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2142 }; 2143}; 2144