1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 * Author: Sam.Shih <sam.shih@mediatek.com> 5 */ 6 7/dts-v1/; 8#include "mt7986a.dtsi" 9 10/ { 11 model = "MediaTek MT7986a RFB"; 12 compatible = "mediatek,mt7986a-rfb"; 13 14 aliases { 15 serial0 = &uart0; 16 }; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 memory@40000000 { 23 device_type = "memory"; 24 reg = <0 0x40000000 0 0x40000000>; 25 }; 26}; 27 28ð { 29 status = "okay"; 30 31 gmac0: mac@0 { 32 compatible = "mediatek,eth-mac"; 33 reg = <0>; 34 phy-mode = "2500base-x"; 35 36 fixed-link { 37 speed = <2500>; 38 full-duplex; 39 pause; 40 }; 41 }; 42 43 mdio: mdio-bus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 }; 47}; 48 49&mdio { 50 switch: switch@0 { 51 compatible = "mediatek,mt7531"; 52 reg = <31>; 53 reset-gpios = <&pio 5 0>; 54 }; 55}; 56 57&switch { 58 ports { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 port@0 { 63 reg = <0>; 64 label = "lan0"; 65 }; 66 67 port@1 { 68 reg = <1>; 69 label = "lan1"; 70 }; 71 72 port@2 { 73 reg = <2>; 74 label = "lan2"; 75 }; 76 77 port@3 { 78 reg = <3>; 79 label = "lan3"; 80 }; 81 82 port@4 { 83 reg = <4>; 84 label = "lan4"; 85 }; 86 87 port@6 { 88 reg = <6>; 89 label = "cpu"; 90 ethernet = <&gmac0>; 91 phy-mode = "2500base-x"; 92 93 fixed-link { 94 speed = <2500>; 95 full-duplex; 96 pause; 97 }; 98 }; 99 }; 100}; 101 102&uart0 { 103 status = "okay"; 104}; 105 106&uart1 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&uart1_pins>; 109 status = "okay"; 110}; 111 112&uart2 { 113 pinctrl-names = "default"; 114 pinctrl-0 = <&uart2_pins>; 115 status = "okay"; 116}; 117 118&pio { 119 uart1_pins: uart1-pins { 120 mux { 121 function = "uart"; 122 groups = "uart1"; 123 }; 124 }; 125 126 uart2_pins: uart2-pins { 127 mux { 128 function = "uart"; 129 groups = "uart2"; 130 }; 131 }; 132}; 133