1/* 2 * Copyright (c) 2016 MediaTek Inc. 3 * Author: Mars.C <mars.cheng@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16 17/ { 18 compatible = "mediatek,mt6755"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 psci { 24 compatible = "arm,psci-0.2"; 25 method = "smc"; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53"; 35 enable-method = "psci"; 36 reg = <0x000>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x001>; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 enable-method = "psci"; 50 reg = <0x002>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 enable-method = "psci"; 57 reg = <0x003>; 58 }; 59 60 cpu4: cpu@100 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x100>; 65 }; 66 67 cpu5: cpu@101 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 enable-method = "psci"; 71 reg = <0x101>; 72 }; 73 74 cpu6: cpu@102 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 enable-method = "psci"; 78 reg = <0x102>; 79 }; 80 81 cpu7: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 enable-method = "psci"; 85 reg = <0x103>; 86 }; 87 }; 88 89 uart_clk: dummy26m { 90 compatible = "fixed-clock"; 91 clock-frequency = <26000000>; 92 #clock-cells = <0>; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupt-parent = <&gic>; 98 interrupts = <GIC_PPI 13 99 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 101 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 103 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 105 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 106 }; 107 108 sysirq: intpol-controller@10200620 { 109 compatible = "mediatek,mt6755-sysirq", 110 "mediatek,mt6577-sysirq"; 111 interrupt-controller; 112 #interrupt-cells = <3>; 113 interrupt-parent = <&gic>; 114 reg = <0 0x10200620 0 0x20>; 115 }; 116 117 gic: interrupt-controller@10231000 { 118 compatible = "arm,gic-400"; 119 #interrupt-cells = <3>; 120 interrupt-parent = <&gic>; 121 interrupt-controller; 122 reg = <0 0x10231000 0 0x1000>, 123 <0 0x10232000 0 0x2000>, 124 <0 0x10234000 0 0x2000>, 125 <0 0x10236000 0 0x2000>; 126 }; 127 128 uart0: serial@11002000 { 129 compatible = "mediatek,mt6755-uart", 130 "mediatek,mt6577-uart"; 131 reg = <0 0x11002000 0 0x400>; 132 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 133 clocks = <&uart_clk>; 134 status = "disabled"; 135 }; 136 137 uart1: serial@11003000 { 138 compatible = "mediatek,mt6755-uart", 139 "mediatek,mt6577-uart"; 140 reg = <0 0x11003000 0 0x400>; 141 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 142 clocks = <&uart_clk>; 143 status = "disabled"; 144 }; 145}; 146