1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 11X11 EVK board"; 13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 14 15 chosen { 16 stdout-path = &lpuart1; 17 }; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 alloc-ranges = <0 0x80000000 0 0x40000000>; 28 size = <0 0x10000000>; 29 linux,cma-default; 30 }; 31 32 vdev0vring0: vdev0vring0@a4000000 { 33 reg = <0 0xa4000000 0 0x8000>; 34 no-map; 35 }; 36 37 vdev0vring1: vdev0vring1@a4008000 { 38 reg = <0 0xa4008000 0 0x8000>; 39 no-map; 40 }; 41 42 vdev1vring0: vdev1vring0@a4010000 { 43 reg = <0 0xa4010000 0 0x8000>; 44 no-map; 45 }; 46 47 vdev1vring1: vdev1vring1@a4018000 { 48 reg = <0 0xa4018000 0 0x8000>; 49 no-map; 50 }; 51 52 rsc_table: rsc-table@2021e000 { 53 reg = <0 0x2021e000 0 0x1000>; 54 no-map; 55 }; 56 57 vdevbuffer: vdevbuffer@a4020000 { 58 compatible = "shared-dma-pool"; 59 reg = <0 0xa4020000 0 0x100000>; 60 no-map; 61 }; 62 63 }; 64 65 reg_vdd_12v: regulator-vdd-12v { 66 compatible = "regulator-fixed"; 67 regulator-name = "VDD_12V"; 68 regulator-min-microvolt = <12000000>; 69 regulator-max-microvolt = <12000000>; 70 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 71 enable-active-high; 72 }; 73 74 reg_vref_1v8: regulator-adc-vref { 75 compatible = "regulator-fixed"; 76 regulator-name = "vref_1v8"; 77 regulator-min-microvolt = <1800000>; 78 regulator-max-microvolt = <1800000>; 79 }; 80 81 reg_audio_pwr: regulator-audio-pwr { 82 compatible = "regulator-fixed"; 83 regulator-name = "audio-pwr"; 84 regulator-min-microvolt = <3300000>; 85 regulator-max-microvolt = <3300000>; 86 gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 87 enable-active-high; 88 }; 89 90 reg_can2_standby: regulator-can2-standby { 91 compatible = "regulator-fixed"; 92 regulator-name = "can2-stby"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; 96 }; 97 98 reg_m2_pwr: regulator-m2-pwr { 99 compatible = "regulator-fixed"; 100 regulator-name = "M.2-power"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 }; 106 107 reg_usdhc2_vmmc: regulator-usdhc2 { 108 compatible = "regulator-fixed"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 111 regulator-name = "VSD_3V3"; 112 regulator-min-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>; 114 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 115 off-on-delay-us = <12000>; 116 enable-active-high; 117 }; 118 119 reg_usdhc3_vmmc: regulator-usdhc3 { 120 compatible = "regulator-fixed"; 121 regulator-name = "WLAN_EN"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <®_m2_pwr>; 125 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 126 /* 127 * IW612 wifi chip needs more delay than other wifi chips to complete 128 * the host interface initialization after power up, otherwise the 129 * internal state of IW612 may be unstable, resulting in the failure of 130 * the SDIO3.0 switch voltage. 131 */ 132 startup-delay-us = <20000>; 133 enable-active-high; 134 }; 135 136 usdhc3_pwrseq: usdhc3_pwrseq { 137 compatible = "mmc-pwrseq-simple"; 138 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 139 }; 140 141 backlight_lvds: backlight-lvds { 142 compatible = "pwm-backlight"; 143 pwms = <&adp5585 0 100000 0>; 144 brightness-levels = <0 100>; 145 num-interpolated-steps = <100>; 146 default-brightness-level = <100>; 147 power-supply = <®_vdd_12v>; 148 enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; 149 status = "disabled"; 150 }; 151 152 bt_sco_codec: bt-sco-codec { 153 compatible = "linux,bt-sco"; 154 #sound-dai-cells = <1>; 155 }; 156 157 sound-bt-sco { 158 compatible = "simple-audio-card"; 159 simple-audio-card,name = "bt-sco-audio"; 160 simple-audio-card,format = "dsp_a"; 161 simple-audio-card,bitclock-inversion; 162 simple-audio-card,frame-master = <&btcpu>; 163 simple-audio-card,bitclock-master = <&btcpu>; 164 165 btcpu: simple-audio-card,cpu { 166 sound-dai = <&sai1>; 167 dai-tdm-slot-num = <2>; 168 dai-tdm-slot-width = <16>; 169 }; 170 171 simple-audio-card,codec { 172 sound-dai = <&bt_sco_codec 1>; 173 }; 174 }; 175 176 sound-micfil { 177 compatible = "fsl,imx-audio-card"; 178 model = "micfil-audio"; 179 180 pri-dai-link { 181 link-name = "micfil hifi"; 182 format = "i2s"; 183 184 cpu { 185 sound-dai = <&micfil>; 186 }; 187 }; 188 }; 189 190 sound-wm8962 { 191 compatible = "fsl,imx-audio-wm8962"; 192 model = "wm8962-audio"; 193 audio-cpu = <&sai3>; 194 audio-codec = <&wm8962>; 195 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 196 audio-routing = 197 "Headphone Jack", "HPOUTL", 198 "Headphone Jack", "HPOUTR", 199 "Ext Spk", "SPKOUTL", 200 "Ext Spk", "SPKOUTR", 201 "AMIC", "MICBIAS", 202 "IN3R", "AMIC", 203 "IN1R", "AMIC"; 204 }; 205 206 sound-xcvr { 207 compatible = "fsl,imx-audio-card"; 208 model = "imx-audio-xcvr"; 209 210 pri-dai-link { 211 link-name = "XCVR PCM"; 212 213 cpu { 214 sound-dai = <&xcvr>; 215 }; 216 }; 217 }; 218}; 219 220&adc1 { 221 vref-supply = <®_vref_1v8>; 222 status = "okay"; 223}; 224 225&cm33 { 226 mbox-names = "tx", "rx", "rxdb"; 227 mboxes = <&mu1 0 1>, 228 <&mu1 1 1>, 229 <&mu1 3 1>; 230 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 231 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 232 status = "okay"; 233}; 234 235&eqos { 236 pinctrl-names = "default", "sleep"; 237 pinctrl-0 = <&pinctrl_eqos>; 238 pinctrl-1 = <&pinctrl_eqos_sleep>; 239 phy-mode = "rgmii-id"; 240 phy-handle = <ðphy1>; 241 status = "okay"; 242 243 mdio { 244 compatible = "snps,dwmac-mdio"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clock-frequency = <5000000>; 248 249 ethphy1: ethernet-phy@1 { 250 reg = <1>; 251 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 252 reset-assert-us = <10000>; 253 reset-deassert-us = <80000>; 254 realtek,clkout-disable; 255 }; 256 }; 257}; 258 259&fec { 260 pinctrl-names = "default", "sleep"; 261 pinctrl-0 = <&pinctrl_fec>; 262 pinctrl-1 = <&pinctrl_fec_sleep>; 263 phy-mode = "rgmii-id"; 264 phy-handle = <ðphy2>; 265 fsl,magic-packet; 266 status = "okay"; 267 268 mdio { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clock-frequency = <5000000>; 272 273 ethphy2: ethernet-phy@2 { 274 reg = <2>; 275 eee-broken-1000t; 276 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 277 reset-assert-us = <10000>; 278 reset-deassert-us = <80000>; 279 realtek,clkout-disable; 280 }; 281 }; 282}; 283 284&flexcan2 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_flexcan2>; 287 xceiver-supply = <®_can2_standby>; 288 status = "okay"; 289}; 290 291&lpi2c1 { 292 clock-frequency = <400000>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_lpi2c1>; 295 status = "okay"; 296 297 wm8962: codec@1a { 298 compatible = "wlf,wm8962"; 299 reg = <0x1a>; 300 clocks = <&clk IMX93_CLK_SAI3_GATE>; 301 DCVDD-supply = <®_audio_pwr>; 302 DBVDD-supply = <®_audio_pwr>; 303 AVDD-supply = <®_audio_pwr>; 304 CPVDD-supply = <®_audio_pwr>; 305 MICVDD-supply = <®_audio_pwr>; 306 PLLVDD-supply = <®_audio_pwr>; 307 SPKVDD1-supply = <®_audio_pwr>; 308 SPKVDD2-supply = <®_audio_pwr>; 309 gpio-cfg = < 310 0x0000 /* 0:Default */ 311 0x0000 /* 1:Default */ 312 0x0000 /* 2:FN_DMICCLK */ 313 0x0000 /* 3:Default */ 314 0x0000 /* 4:FN_DMICCDAT */ 315 0x0000 /* 5:Default */ 316 >; 317 }; 318 319 inertial-meter@6a { 320 compatible = "st,lsm6dso"; 321 reg = <0x6a>; 322 }; 323}; 324 325&lpi2c2 { 326 clock-frequency = <400000>; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_lpi2c2>; 329 status = "okay"; 330 331 pcal6524: gpio@22 { 332 compatible = "nxp,pcal6524"; 333 reg = <0x22>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_pcal6524>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 interrupt-parent = <&gpio3>; 341 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 342 }; 343 344 pmic@25 { 345 compatible = "nxp,pca9451a"; 346 reg = <0x25>; 347 interrupt-parent = <&pcal6524>; 348 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 349 350 regulators { 351 buck1: BUCK1 { 352 regulator-name = "BUCK1"; 353 regulator-min-microvolt = <610000>; 354 regulator-max-microvolt = <950000>; 355 regulator-boot-on; 356 regulator-always-on; 357 regulator-ramp-delay = <3125>; 358 }; 359 360 buck2: BUCK2 { 361 regulator-name = "BUCK2"; 362 regulator-min-microvolt = <600000>; 363 regulator-max-microvolt = <670000>; 364 regulator-boot-on; 365 regulator-always-on; 366 regulator-ramp-delay = <3125>; 367 }; 368 369 buck4: BUCK4 { 370 regulator-name = "BUCK4"; 371 regulator-min-microvolt = <1620000>; 372 regulator-max-microvolt = <3400000>; 373 regulator-boot-on; 374 regulator-always-on; 375 }; 376 377 buck5: BUCK5 { 378 regulator-name = "BUCK5"; 379 regulator-min-microvolt = <1620000>; 380 regulator-max-microvolt = <3400000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 385 buck6: BUCK6 { 386 regulator-name = "BUCK6"; 387 regulator-min-microvolt = <1060000>; 388 regulator-max-microvolt = <1140000>; 389 regulator-boot-on; 390 regulator-always-on; 391 }; 392 393 ldo1: LDO1 { 394 regulator-name = "LDO1"; 395 regulator-min-microvolt = <1620000>; 396 regulator-max-microvolt = <1980000>; 397 regulator-boot-on; 398 regulator-always-on; 399 }; 400 401 ldo4: LDO4 { 402 regulator-name = "LDO4"; 403 regulator-min-microvolt = <800000>; 404 regulator-max-microvolt = <840000>; 405 regulator-boot-on; 406 regulator-always-on; 407 }; 408 409 ldo5: LDO5 { 410 regulator-name = "LDO5"; 411 regulator-min-microvolt = <1800000>; 412 regulator-max-microvolt = <3300000>; 413 regulator-boot-on; 414 regulator-always-on; 415 }; 416 }; 417 }; 418 419 adp5585: io-expander@34 { 420 compatible = "adi,adp5585-00", "adi,adp5585"; 421 reg = <0x34>; 422 vdd-supply = <&buck4>; 423 gpio-controller; 424 #gpio-cells = <2>; 425 gpio-reserved-ranges = <5 1>; 426 #pwm-cells = <3>; 427 }; 428}; 429 430&lpi2c3 { 431 clock-frequency = <400000>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_lpi2c3>; 434 status = "okay"; 435 436 adp5585_isp: io-expander@34 { 437 compatible = "adi,adp5585-01", "adi,adp5585"; 438 reg = <0x34>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 #pwm-cells = <3>; 442 }; 443 444 ptn5110: tcpc@50 { 445 compatible = "nxp,ptn5110", "tcpci"; 446 reg = <0x50>; 447 interrupt-parent = <&gpio3>; 448 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 449 450 typec1_con: connector { 451 compatible = "usb-c-connector"; 452 label = "USB-C"; 453 power-role = "dual"; 454 data-role = "dual"; 455 try-power-role = "sink"; 456 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 457 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 458 PDO_VAR(5000, 20000, 3000)>; 459 op-sink-microwatt = <15000000>; 460 self-powered; 461 462 ports { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 port@0 { 467 reg = <0>; 468 469 typec1_dr_sw: endpoint { 470 remote-endpoint = <&usb1_drd_sw>; 471 }; 472 }; 473 }; 474 }; 475 }; 476 477 ptn5110_2: tcpc@51 { 478 compatible = "nxp,ptn5110", "tcpci"; 479 reg = <0x51>; 480 interrupt-parent = <&gpio3>; 481 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 482 483 typec2_con: connector { 484 compatible = "usb-c-connector"; 485 label = "USB-C"; 486 power-role = "dual"; 487 data-role = "dual"; 488 try-power-role = "sink"; 489 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 490 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 491 PDO_VAR(5000, 20000, 3000)>; 492 op-sink-microwatt = <15000000>; 493 self-powered; 494 495 ports { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 499 port@0 { 500 reg = <0>; 501 502 typec2_dr_sw: endpoint { 503 remote-endpoint = <&usb2_drd_sw>; 504 }; 505 }; 506 }; 507 }; 508 }; 509 510 pcf2131: rtc@53 { 511 compatible = "nxp,pcf2131"; 512 reg = <0x53>; 513 interrupt-parent = <&pcal6524>; 514 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 515 }; 516}; 517 518&lpuart1 { /* console */ 519 pinctrl-names = "default"; 520 pinctrl-0 = <&pinctrl_uart1>; 521 status = "okay"; 522}; 523 524&lpuart5 { 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_uart5>; 527 status = "okay"; 528 529 bluetooth { 530 compatible = "nxp,88w8987-bt"; 531 }; 532}; 533 534&micfil { 535 pinctrl-names = "default", "sleep"; 536 pinctrl-0 = <&pinctrl_pdm>; 537 pinctrl-1 = <&pinctrl_pdm_sleep>; 538 assigned-clocks = <&clk IMX93_CLK_PDM>; 539 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 540 assigned-clock-rates = <49152000>; 541 status = "okay"; 542}; 543 544&mu1 { 545 status = "okay"; 546}; 547 548&mu2 { 549 status = "okay"; 550}; 551 552&sai1 { 553 pinctrl-names = "default", "sleep"; 554 pinctrl-0 = <&pinctrl_sai1>; 555 pinctrl-1 = <&pinctrl_sai1_sleep>; 556 assigned-clocks = <&clk IMX93_CLK_SAI1>; 557 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 558 assigned-clock-rates = <12288000>; 559 fsl,sai-mclk-direction-output; 560 status = "okay"; 561}; 562 563&sai3 { 564 pinctrl-names = "default", "sleep"; 565 pinctrl-0 = <&pinctrl_sai3>; 566 pinctrl-1 = <&pinctrl_sai3_sleep>; 567 assigned-clocks = <&clk IMX93_CLK_SAI3>; 568 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 569 assigned-clock-rates = <12288000>; 570 fsl,sai-mclk-direction-output; 571 status = "okay"; 572}; 573 574&usbotg1 { 575 dr_mode = "otg"; 576 hnp-disable; 577 srp-disable; 578 adp-disable; 579 usb-role-switch; 580 disable-over-current; 581 samsung,picophy-pre-emp-curr-control = <3>; 582 samsung,picophy-dc-vol-level-adjust = <7>; 583 status = "okay"; 584 585 port { 586 usb1_drd_sw: endpoint { 587 remote-endpoint = <&typec1_dr_sw>; 588 }; 589 }; 590}; 591 592&usbotg2 { 593 dr_mode = "otg"; 594 hnp-disable; 595 srp-disable; 596 adp-disable; 597 usb-role-switch; 598 disable-over-current; 599 samsung,picophy-pre-emp-curr-control = <3>; 600 samsung,picophy-dc-vol-level-adjust = <7>; 601 status = "okay"; 602 603 port { 604 usb2_drd_sw: endpoint { 605 remote-endpoint = <&typec2_dr_sw>; 606 }; 607 }; 608}; 609 610&usdhc1 { 611 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 612 pinctrl-0 = <&pinctrl_usdhc1>; 613 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 614 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 615 bus-width = <8>; 616 non-removable; 617 status = "okay"; 618}; 619 620&usdhc2 { 621 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 622 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 623 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 624 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 625 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 626 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 627 vmmc-supply = <®_usdhc2_vmmc>; 628 bus-width = <4>; 629 status = "okay"; 630 no-mmc; 631}; 632 633&usdhc3 { 634 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 635 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 636 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 637 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 638 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 639 mmc-pwrseq = <&usdhc3_pwrseq>; 640 vmmc-supply = <®_usdhc3_vmmc>; 641 bus-width = <4>; 642 keep-power-in-suspend; 643 non-removable; 644 wakeup-source; 645 status = "okay"; 646}; 647 648&wdog3 { 649 pinctrl-names = "default"; 650 pinctrl-0 = <&pinctrl_wdog>; 651 fsl,ext-reset-output; 652 status = "okay"; 653}; 654 655&xcvr { 656 pinctrl-names = "default", "sleep"; 657 pinctrl-0 = <&pinctrl_spdif>; 658 pinctrl-1 = <&pinctrl_spdif_sleep>; 659 assigned-clocks = <&clk IMX93_CLK_SPDIF>, 660 <&clk IMX93_CLK_AUDIO_XCVR>; 661 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, 662 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 663 assigned-clock-rates = <12288000>, <200000000>; 664 status = "okay"; 665}; 666 667&iomuxc { 668 pinctrl_eqos: eqosgrp { 669 fsl,pins = < 670 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 671 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 672 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 673 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 674 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 675 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 676 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 677 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 678 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 679 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 680 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 681 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 682 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 683 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 684 >; 685 }; 686 687 pinctrl_eqos_sleep: eqossleepgrp { 688 fsl,pins = < 689 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 690 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 691 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 692 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 693 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 694 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 695 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 696 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 697 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 698 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 699 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 700 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 701 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 702 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 703 >; 704 }; 705 706 pinctrl_fec: fecgrp { 707 fsl,pins = < 708 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 709 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 710 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 711 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 712 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 713 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 714 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 715 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 716 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 717 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 718 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 719 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 720 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 721 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 722 >; 723 }; 724 725 pinctrl_fec_sleep: fecsleepgrp { 726 fsl,pins = < 727 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 728 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 729 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 730 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 731 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 732 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 733 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 734 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 735 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 736 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 737 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 738 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 739 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 740 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 741 >; 742 }; 743 744 pinctrl_flexcan2: flexcan2grp { 745 fsl,pins = < 746 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 747 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 748 >; 749 }; 750 751 pinctrl_uart1: uart1grp { 752 fsl,pins = < 753 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 754 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 755 >; 756 }; 757 758 pinctrl_uart5: uart5grp { 759 fsl,pins = < 760 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 761 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 762 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 763 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 764 >; 765 }; 766 767 pinctrl_lpi2c1: lpi2c1grp { 768 fsl,pins = < 769 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 770 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 771 >; 772 }; 773 774 pinctrl_lpi2c2: lpi2c2grp { 775 fsl,pins = < 776 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 777 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 778 >; 779 }; 780 781 pinctrl_lpi2c3: lpi2c3grp { 782 fsl,pins = < 783 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 784 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 785 >; 786 }; 787 788 pinctrl_pcal6524: pcal6524grp { 789 fsl,pins = < 790 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 791 >; 792 }; 793 794 pinctrl_pdm: pdmgrp { 795 fsl,pins = < 796 MX93_PAD_PDM_CLK__PDM_CLK 0x31e 797 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 798 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 799 >; 800 }; 801 802 pinctrl_pdm_sleep: pdmsleepgrp { 803 fsl,pins = < 804 MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e 805 MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e 806 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 807 >; 808 }; 809 810 pinctrl_sai1: sai1grp { 811 fsl,pins = < 812 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 813 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 814 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 815 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 816 >; 817 }; 818 819 pinctrl_sai1_sleep: sai1sleepgrp { 820 fsl,pins = < 821 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e 822 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e 823 MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e 824 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e 825 >; 826 }; 827 828 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 829 pinctrl_usdhc1: usdhc1grp { 830 fsl,pins = < 831 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 832 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 833 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 834 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 835 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 836 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 837 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 838 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 839 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 840 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 841 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 842 >; 843 }; 844 845 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 846 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 847 fsl,pins = < 848 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 849 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 850 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 851 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 852 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 853 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 854 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 855 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 856 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 857 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 858 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 859 >; 860 }; 861 862 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 863 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 864 fsl,pins = < 865 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 866 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 867 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 868 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 869 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 870 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 871 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 872 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 873 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 874 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 875 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 876 >; 877 }; 878 879 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 880 fsl,pins = < 881 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 882 >; 883 }; 884 885 pinctrl_sai3: sai3grp { 886 fsl,pins = < 887 MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 888 MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 889 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 890 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 891 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 892 >; 893 }; 894 895 pinctrl_sai3_sleep: sai3sleepgrp { 896 fsl,pins = < 897 MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e 898 MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e 899 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e 900 MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e 901 MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e 902 >; 903 }; 904 905 pinctrl_spdif: spdifgrp { 906 fsl,pins = < 907 MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e 908 MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e 909 >; 910 }; 911 912 pinctrl_spdif_sleep: spdifsleepgrp { 913 fsl,pins = < 914 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 915 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 916 >; 917 }; 918 919 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 920 fsl,pins = < 921 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 922 >; 923 }; 924 925 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 926 fsl,pins = < 927 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 928 >; 929 }; 930 931 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 932 pinctrl_usdhc2: usdhc2grp { 933 fsl,pins = < 934 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 935 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 936 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 937 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 938 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 939 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 940 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 941 >; 942 }; 943 944 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 945 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 946 fsl,pins = < 947 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 948 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 949 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 950 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 951 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 952 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 953 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 954 >; 955 }; 956 957 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 958 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 959 fsl,pins = < 960 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 961 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 962 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 963 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 964 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 965 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 966 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 967 >; 968 }; 969 970 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 971 fsl,pins = < 972 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 973 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 974 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 975 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 976 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 977 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 978 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 979 >; 980 }; 981 982 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 983 pinctrl_usdhc3: usdhc3grp { 984 fsl,pins = < 985 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 986 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 987 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 988 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 989 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 990 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 991 >; 992 }; 993 994 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 995 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 996 fsl,pins = < 997 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 998 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 999 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 1000 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 1001 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 1002 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 1003 >; 1004 }; 1005 1006 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 1007 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1008 fsl,pins = < 1009 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 1010 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 1011 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 1012 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 1013 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 1014 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 1015 >; 1016 }; 1017 1018 pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { 1019 fsl,pins = < 1020 MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e 1021 MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e 1022 MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e 1023 MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e 1024 MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e 1025 MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e 1026 >; 1027 }; 1028 1029 pinctrl_usdhc3_wlan: usdhc3wlangrp { 1030 fsl,pins = < 1031 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 1032 >; 1033 }; 1034 1035 pinctrl_wdog: wdoggrp { 1036 fsl,pins = < 1037 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 1038 >; 1039 }; 1040}; 1041