1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 chassis-type = "embedded"; 19 20 chosen { 21 stdout-path = &uart4; 22 }; 23 24 iio-hwmon { 25 compatible = "iio-hwmon"; 26 io-channels = <&adc 0>, <&adc 1>; 27 }; 28 29 aliases { 30 mmc0 = &usdhc3; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc1; 33 rtc0 = &pcf85063; 34 rtc1 = &snvs_rtc; 35 spi0 = &flexspi; 36 spi1 = &ecspi1; 37 spi2 = &ecspi2; 38 spi3 = &ecspi3; 39 }; 40 41 backlight_lvds: backlight { 42 compatible = "pwm-backlight"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_backlight>; 45 pwms = <&pwm2 0 5000000 0>; 46 brightness-levels = <0 4 8 16 32 64 128 255>; 47 default-brightness-level = <7>; 48 power-supply = <®_vcc_12v0>; 49 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 50 status = "disabled"; 51 }; 52 53 clk_xtal25: clk-xtal25 { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <25000000>; 57 }; 58 59 connector { 60 compatible = "gpio-usb-b-connector", "usb-b-connector"; 61 type = "micro"; 62 label = "X29"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_usbcon0>; 65 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 66 67 port { 68 usb_dr_connector: endpoint { 69 remote-endpoint = <&usb3_dwc>; 70 }; 71 }; 72 }; 73 74 fan0: pwm-fan { 75 compatible = "pwm-fan"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_pwmfan>; 78 fan-supply = <®_pwm_fan>; 79 #cooling-cells = <2>; 80 /* typical 25 kHz -> 40.000 nsec */ 81 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; 82 cooling-levels = <0 32 64 128 196 240>; 83 pulses-per-revolution = <2>; 84 interrupt-parent = <&gpio5>; 85 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 86 status = "disabled"; 87 }; 88 89 gpio-keys { 90 compatible = "gpio-keys"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_gpiobutton>; 93 autorepeat; 94 95 switch-1 { 96 label = "S12"; 97 linux,code = <BTN_0>; 98 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 99 wakeup-source; 100 }; 101 102 switch-2 { 103 label = "S13"; 104 linux,code = <BTN_1>; 105 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 106 wakeup-source; 107 }; 108 }; 109 110 gpio-leds { 111 compatible = "gpio-leds"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_gpioled>; 114 115 led-0 { 116 color = <LED_COLOR_ID_GREEN>; 117 function = LED_FUNCTION_STATUS; 118 function-enumerator = <0>; 119 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 120 linux,default-trigger = "default-on"; 121 }; 122 123 led-1 { 124 color = <LED_COLOR_ID_GREEN>; 125 function = LED_FUNCTION_HEARTBEAT; 126 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 127 linux,default-trigger = "heartbeat"; 128 }; 129 130 led-2 { 131 color = <LED_COLOR_ID_YELLOW>; 132 function = LED_FUNCTION_STATUS; 133 function-enumerator = <1>; 134 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 135 }; 136 }; 137 138 hdmi-connector { 139 compatible = "hdmi-connector"; 140 label = "X44"; 141 type = "a"; 142 143 port { 144 hdmi_connector_in: endpoint { 145 remote-endpoint = <&hdmi_tx_out>; 146 }; 147 }; 148 }; 149 150 display: display { 151 /* 152 * Display is not fixed, so compatible has to be added from 153 * DT overlay 154 */ 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_lvdsdisplay>; 157 power-supply = <®_vcc_3v3>; 158 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 159 backlight = <&backlight_lvds>; 160 status = "disabled"; 161 }; 162 163 reg_pwm_fan: regulator-pwm-fan { 164 compatible = "regulator-fixed"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_regpwmfan>; 167 regulator-name = "FAN_PWR"; 168 regulator-min-microvolt = <12000000>; 169 regulator-max-microvolt = <12000000>; 170 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 171 enable-active-high; 172 vin-supply = <®_vcc_12v0>; 173 }; 174 175 reg_usdhc2_vmmc: regulator-usdhc2 { 176 compatible = "regulator-fixed"; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 179 regulator-name = "VSD_3V3"; 180 regulator-min-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>; 182 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 183 enable-active-high; 184 startup-delay-us = <100>; 185 off-on-delay-us = <12000>; 186 }; 187 188 reg_vcc_12v0: regulator-12v0 { 189 compatible = "regulator-fixed"; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_reg12v0>; 192 regulator-name = "VCC_12V0"; 193 regulator-min-microvolt = <12000000>; 194 regulator-max-microvolt = <12000000>; 195 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 196 enable-active-high; 197 }; 198 199 reg_vcc_1v8: regulator-1v8 { 200 compatible = "regulator-fixed"; 201 regulator-name = "VCC_1V8"; 202 regulator-min-microvolt = <1800000>; 203 regulator-max-microvolt = <1800000>; 204 }; 205 206 reg_vcc_3v3: regulator-3v3 { 207 compatible = "regulator-fixed"; 208 regulator-name = "VCC_3V3"; 209 regulator-min-microvolt = <3300000>; 210 regulator-max-microvolt = <3300000>; 211 }; 212 213 reg_vcc_5v0: regulator-5v0 { 214 compatible = "regulator-fixed"; 215 regulator-name = "VCC_5V0"; 216 regulator-min-microvolt = <5000000>; 217 regulator-max-microvolt = <5000000>; 218 }; 219 220 reserved-memory { 221 #address-cells = <2>; 222 #size-cells = <2>; 223 ranges; 224 225 /* global autoconfigured region for contiguous allocations */ 226 linux,cma { 227 compatible = "shared-dma-pool"; 228 reusable; 229 size = <0 0x38000000>; 230 alloc-ranges = <0 0x40000000 0 0xB0000000>; 231 linux,cma-default; 232 }; 233 }; 234 235 sound { 236 compatible = "fsl,imx-audio-tlv320aic32x4"; 237 model = "tqm-tlv320aic32"; 238 audio-asrc = <&easrc>; 239 audio-cpu = <&sai3>; 240 audio-codec = <&tlv320aic3x04>; 241 }; 242 243 thermal-zones { 244 soc-thermal { 245 trips { 246 soc_active0: trip-active0 { 247 temperature = <40000>; 248 hysteresis = <5000>; 249 type = "active"; 250 }; 251 252 soc_active1: trip-active1 { 253 temperature = <48000>; 254 hysteresis = <3000>; 255 type = "active"; 256 }; 257 258 soc_active2: trip-active2 { 259 temperature = <60000>; 260 hysteresis = <10000>; 261 type = "active"; 262 }; 263 }; 264 265 cooling-maps { 266 map1 { 267 trip = <&soc_active0>; 268 cooling-device = <&fan0 1 1>; 269 }; 270 271 map2 { 272 trip = <&soc_active1>; 273 cooling-device = <&fan0 2 2>; 274 }; 275 276 map3 { 277 trip = <&soc_active2>; 278 cooling-device = <&fan0 3 3>; 279 }; 280 }; 281 }; 282 }; 283}; 284 285&ecspi1 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_ecspi1>; 288 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 289 status = "okay"; 290}; 291 292&ecspi2 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_ecspi2>; 295 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 296 status = "okay"; 297}; 298 299&ecspi3 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_ecspi3>; 302 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 303 status = "okay"; 304 305 adc: adc@0 { 306 reg = <0>; 307 compatible = "microchip,mcp3202"; 308 /* 100 ksps * 18 */ 309 spi-max-frequency = <1800000>; 310 vref-supply = <®_vcc_3v3>; 311 #io-channel-cells = <1>; 312 }; 313}; 314 315&eqos { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 318 phy-mode = "rgmii-id"; 319 phy-handle = <ðphy3>; 320 status = "okay"; 321 322 mdio { 323 compatible = "snps,dwmac-mdio"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 ethphy3: ethernet-phy@3 { 328 compatible = "ethernet-phy-ieee802.3-c22"; 329 reg = <3>; 330 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 331 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 332 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 333 ti,dp83867-rxctrl-strap-quirk; 334 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 335 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 336 reset-assert-us = <500000>; 337 reset-deassert-us = <50000>; 338 enet-phy-lane-no-swap; 339 interrupt-parent = <&gpio4>; 340 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 341 }; 342 }; 343}; 344 345&fec { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 348 phy-mode = "rgmii-id"; 349 phy-handle = <ðphy0>; 350 fsl,magic-packet; 351 status = "okay"; 352 353 mdio { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 ethphy0: ethernet-phy@0 { 358 compatible = "ethernet-phy-ieee802.3-c22"; 359 reg = <0>; 360 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 361 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 362 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 363 ti,dp83867-rxctrl-strap-quirk; 364 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 365 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 366 reset-assert-us = <500000>; 367 reset-deassert-us = <50000>; 368 enet-phy-lane-no-swap; 369 interrupt-parent = <&gpio4>; 370 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 371 }; 372 }; 373}; 374 375&flexcan1 { 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_flexcan1>; 378 xceiver-supply = <®_vcc_3v3>; 379 status = "okay"; 380}; 381 382&flexcan2 { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_flexcan2>; 385 xceiver-supply = <®_vcc_3v3>; 386 status = "okay"; 387}; 388 389&gpio1 { 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_gpio1>; 392 393 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 394 "", "", "GPO2", "GPI0", 395 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 396 "OTG_PWR", "", "GPI2", "GPI3", 397 "", "", "", "", 398 "", "", "", "", 399 "", "", "", "", 400 "", "", "", ""; 401}; 402 403&gpio2 { 404 pinctrl-names = "default"; 405 pinctrl-0 = <&pinctrl_hoggpio2>; 406 407 gpio-line-names = "", "", "", "", 408 "", "", "VCC12V_EN", "PERST#", 409 "", "", "CLKREQ#", "PEWAKE#", 410 "USDHC2_CD", "", "", "", 411 "", "", "", "V_SD3V3_EN", 412 "", "", "", "", 413 "", "", "", "", 414 "", "", "", ""; 415 416 perst-hog { 417 gpio-hog; 418 gpios = <7 0>; 419 output-high; 420 line-name = "PERST#"; 421 }; 422 423 clkreq-hog { 424 gpio-hog; 425 gpios = <10 0>; 426 input; 427 line-name = "CLKREQ#"; 428 }; 429 430 pewake-hog { 431 gpio-hog; 432 gpios = <11 0>; 433 input; 434 line-name = "PEWAKE#"; 435 }; 436}; 437 438&gpio3 { 439 gpio-line-names = "", "", "", "", 440 "", "", "", "", 441 "", "", "", "", 442 "", "", "LVDS0_RESET#", "", 443 "", "", "", "LVDS0_BLT_EN", 444 "LVDS0_PWR_EN", "", "", "", 445 "", "", "", "", 446 "", "", "", ""; 447}; 448 449&gpio4 { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_gpio4>; 452 453 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 454 "", "", "", "", 455 "", "", "", "", 456 "", "", "", "", 457 "", "", "DP_IRQ", "DSI_EN", 458 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 459 "", "", "", "FAN_PWR", 460 "RTC_EVENT#", "CODEC_RST#", "", ""; 461 462 pcie-refclkreq-hog { 463 gpio-hog; 464 gpios = <22 0>; 465 output-high; 466 line-name = "PCIE_REFCLK_OE#"; 467 }; 468}; 469 470&gpio5 { 471 gpio-line-names = "", "", "", "LED2", 472 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 473 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 474 "", "ECSPI2_SS0", "", "", 475 "", "", "", "", 476 "", "", "", "", 477 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 478 "", "", "", ""; 479}; 480 481&hdmi_pvi { 482 status = "okay"; 483}; 484 485&hdmi_tx { 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pinctrl_hdmi>; 488 status = "okay"; 489 490 ports { 491 port@1 { 492 hdmi_tx_out: endpoint { 493 remote-endpoint = <&hdmi_connector_in>; 494 }; 495 }; 496 }; 497}; 498 499&hdmi_tx_phy { 500 status = "okay"; 501}; 502 503&i2c2 { 504 clock-frequency = <384000>; 505 pinctrl-names = "default", "gpio"; 506 pinctrl-0 = <&pinctrl_i2c2>; 507 pinctrl-1 = <&pinctrl_i2c2_gpio>; 508 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 509 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 510 status = "okay"; 511 512 tlv320aic3x04: audio-codec@18 { 513 compatible = "ti,tlv320aic32x4"; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pinctrl_tlv320aic3x04>; 516 reg = <0x18>; 517 clock-names = "mclk"; 518 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 519 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; 520 iov-supply = <®_vcc_1v8>; 521 ldoin-supply = <®_vcc_3v3>; 522 }; 523 524 se97_1c: temperature-sensor@1c { 525 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 526 reg = <0x1c>; 527 }; 528 529 at24c02_54: eeprom@54 { 530 compatible = "nxp,se97b", "atmel,24c02"; 531 reg = <0x54>; 532 pagesize = <16>; 533 vcc-supply = <®_vcc_3v3>; 534 }; 535 536 pcieclk: clock-generator@6a { 537 compatible = "renesas,9fgv0241"; 538 reg = <0x6a>; 539 clocks = <&clk_xtal25>; 540 #clock-cells = <1>; 541 }; 542}; 543 544&i2c4 { 545 clock-frequency = <384000>; 546 pinctrl-names = "default", "gpio"; 547 pinctrl-0 = <&pinctrl_i2c4>; 548 pinctrl-1 = <&pinctrl_i2c4_gpio>; 549 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 550 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 551 status = "okay"; 552}; 553 554&i2c6 { 555 clock-frequency = <384000>; 556 pinctrl-names = "default", "gpio"; 557 pinctrl-0 = <&pinctrl_i2c6>; 558 pinctrl-1 = <&pinctrl_i2c6_gpio>; 559 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 560 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 561 status = "okay"; 562}; 563 564&lcdif3 { 565 status = "okay"; 566}; 567 568&pcf85063 { 569 /* RTC_EVENT# is connected on MBa8MPxL */ 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_pcf85063>; 572 interrupt-parent = <&gpio4>; 573 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 574}; 575 576&pcie_phy { 577 fsl,clkreq-unsupported; 578 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 579 clocks = <&pcieclk 0>; 580 clock-names = "ref"; 581 status = "okay"; 582}; 583 584&pcie { 585 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 586 <&clk IMX8MP_CLK_HSIO_AXI>, 587 <&clk IMX8MP_CLK_PCIE_ROOT>; 588 clock-names = "pcie", "pcie_bus", "pcie_aux"; 589 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 590 assigned-clock-rates = <10000000>; 591 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 592 status = "okay"; 593}; 594 595&pwm2 { 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pinctrl_pwm2>; 598 status = "disabled"; 599}; 600 601&pwm3 { 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_pwm3>; 604 status = "okay"; 605}; 606 607®_usdhc2_vqmmc { 608 status = "okay"; 609}; 610 611&sai3 { 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pinctrl_sai3>; 614 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 615 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 616 assigned-clock-rates = <12288000>; 617 fsl,sai-mclk-direction-output; 618 status = "okay"; 619}; 620 621&snvs_pwrkey { 622 status = "okay"; 623}; 624 625&uart1 { 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_uart1>; 628 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 629 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 630 status = "okay"; 631}; 632 633&uart2 { 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pinctrl_uart2>; 636 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 637 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 638 status = "okay"; 639}; 640 641&uart3 { 642 pinctrl-names = "default"; 643 pinctrl-0 = <&pinctrl_uart3>; 644 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 645 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 646 status = "okay"; 647}; 648 649&uart4 { 650 /* console */ 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_uart4>; 653 status = "okay"; 654}; 655 656&usb3_0 { 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pinctrl_usb0>; 659 fsl,over-current-active-low; 660 status = "okay"; 661}; 662 663&usb3_1 { 664 fsl,disable-port-power-control; 665 fsl,permanently-attached; 666 status = "okay"; 667}; 668 669&usb3_phy0 { 670 vbus-supply = <®_vcc_5v0>; 671 status = "okay"; 672}; 673 674&usb3_phy1 { 675 vbus-supply = <®_vcc_5v0>; 676 status = "okay"; 677}; 678 679&usb_dwc3_0 { 680 /* dual role is implemented, but not a full featured OTG */ 681 hnp-disable; 682 srp-disable; 683 adp-disable; 684 dr_mode = "otg"; 685 usb-role-switch; 686 role-switch-default-mode = "peripheral"; 687 status = "okay"; 688 689 port { 690 usb3_dwc: endpoint { 691 remote-endpoint = <&usb_dr_connector>; 692 }; 693 }; 694}; 695 696&usb_dwc3_1 { 697 dr_mode = "host"; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_usbhub>; 702 status = "okay"; 703 704 hub_2_0: hub@1 { 705 compatible = "usb451,8142"; 706 reg = <1>; 707 peer-hub = <&hub_3_0>; 708 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 709 vdd-supply = <®_vcc_3v3>; 710 }; 711 712 hub_3_0: hub@2 { 713 compatible = "usb451,8140"; 714 reg = <2>; 715 peer-hub = <&hub_2_0>; 716 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 717 vdd-supply = <®_vcc_3v3>; 718 }; 719}; 720 721&usdhc2 { 722 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 723 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 724 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 725 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 726 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 727 vmmc-supply = <®_usdhc2_vmmc>; 728 no-mmc; 729 no-sdio; 730 disable-wp; 731 bus-width = <4>; 732 status = "okay"; 733}; 734 735&iomuxc { 736 pinctrl_backlight: backlightgrp { 737 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 738 }; 739 740 pinctrl_flexcan1: flexcan1grp { 741 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 742 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 743 }; 744 745 pinctrl_flexcan2: flexcan2grp { 746 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 747 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 748 }; 749 750 /* only on X57, primary used as CSI0 control signals */ 751 pinctrl_ecspi1: ecspi1grp { 752 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 753 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 754 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 755 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 756 }; 757 758 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 759 pinctrl_ecspi2: ecspi2grp { 760 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 761 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 762 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 763 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 764 }; 765 766 pinctrl_ecspi3: ecspi3grp { 767 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 768 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 769 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 770 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 771 }; 772 773 pinctrl_eqos: eqosgrp { 774 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 775 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 776 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 777 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 778 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 779 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 780 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 781 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 782 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 783 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 784 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 785 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 786 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 787 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 788 }; 789 790 pinctrl_eqos_event: eqosevtgrp { 791 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 792 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 793 }; 794 795 pinctrl_eqos_phy: eqosphygrp { 796 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 797 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 798 }; 799 800 pinctrl_fec: fecgrp { 801 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 802 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 803 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 804 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 805 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 806 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 807 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 808 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 809 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 810 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 811 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 812 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 813 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 814 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 815 }; 816 817 pinctrl_fec_event: fecevtgrp { 818 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 819 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 820 }; 821 822 pinctrl_fec_phy: fecphygrp { 823 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 824 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 825 }; 826 827 pinctrl_fec_phyalt: fecphyaltgrp { 828 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 829 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 830 }; 831 832 pinctrl_gpiobutton: gpiobuttongrp { 833 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 834 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 835 }; 836 837 pinctrl_gpioled: gpioledgrp { 838 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 839 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 840 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 841 }; 842 843 pinctrl_gpio1: gpio1grp { 844 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 845 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 846 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 847 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 848 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 849 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 850 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 851 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 852 }; 853 854 pinctrl_gpio4: gpio4grp { 855 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 856 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 857 }; 858 859 pinctrl_hdmi: hdmigrp { 860 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 861 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 862 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 863 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 864 }; 865 866 pinctrl_hoggpio2: hoggpio2grp { 867 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 868 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 869 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 870 }; 871 872 pinctrl_i2c2: i2c2grp { 873 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 874 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 875 }; 876 877 pinctrl_i2c2_gpio: i2c2-gpiogrp { 878 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 879 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 880 }; 881 882 pinctrl_i2c4: i2c4grp { 883 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 884 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 885 }; 886 887 pinctrl_i2c4_gpio: i2c4-gpiogrp { 888 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 889 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 890 }; 891 892 pinctrl_i2c6: i2c6grp { 893 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 894 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 895 }; 896 897 pinctrl_i2c6_gpio: i2c6-gpiogrp { 898 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 899 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 900 }; 901 902 pinctrl_lvdsdisplay: lvdsdisplaygrp { 903 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 904 }; 905 906 pinctrl_pcf85063: pcf85063grp { 907 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 908 }; 909 910 /* LVDS Backlight */ 911 pinctrl_pwm2: pwm2grp { 912 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 913 }; 914 915 /* FAN */ 916 pinctrl_pwm3: pwm3grp { 917 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 918 }; 919 920 pinctrl_pwmfan: pwmfangrp { 921 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ 922 }; 923 924 pinctrl_reg12v0: reg12v0grp { 925 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 926 }; 927 928 pinctrl_regpwmfan: regpwmfangrp { 929 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; 930 }; 931 932 pinctrl_sai3: sai3grp { 933 fsl,pins = < 934 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 935 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 936 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 937 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 938 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94 939 >; 940 }; 941 942 pinctrl_tlv320aic3x04: tlv320aic3x04grp { 943 fsl,pins = < 944 /* CODEC RST# */ 945 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180 946 >; 947 }; 948 949 /* X61 */ 950 pinctrl_uart1: uart1grp { 951 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 952 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 953 }; 954 955 /* X61 */ 956 pinctrl_uart2: uart2grp { 957 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 958 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 959 }; 960 961 pinctrl_uart3: uart3grp { 962 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 963 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 964 }; 965 966 pinctrl_uart4: uart4grp { 967 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 968 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 969 }; 970 971 pinctrl_usb0: usb0grp { 972 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 973 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 974 }; 975 976 pinctrl_usbcon0: usb0congrp { 977 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 978 }; 979 980 pinctrl_usbhub: usbhubgrp { 981 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 982 }; 983 984 pinctrl_usdhc2: usdhc2grp { 985 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 986 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 987 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 988 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 989 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 990 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 991 }; 992 993 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 994 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 995 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 996 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 997 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 998 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 999 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1000 }; 1001 1002 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1003 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1004 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1005 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1006 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1007 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1008 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1009 }; 1010 1011 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1012 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 1013 }; 1014}; 1015