1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree fragment for LS1028A QDS board, serdes 7777 4 * 5 * Copyright 2019-2021 NXP 6 * 7 * Requires a LS1028A QDS board without lane B rework. 8 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing 9 * disabled, plugged in slot 1. 10 */ 11 12/dts-v1/; 13/plugin/; 14 15/ { 16 fragment@0 { 17 target = <&mdio_slot1>; 18 19 __overlay__ { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 /* 4 ports on AQR412 */ 24 slot1_sxgmii0: ethernet-phy@0 { 25 reg = <0x0>; 26 compatible = "ethernet-phy-ieee802.3-c45"; 27 }; 28 29 slot1_sxgmii1: ethernet-phy@1 { 30 reg = <0x1>; 31 compatible = "ethernet-phy-ieee802.3-c45"; 32 }; 33 34 slot1_sxgmii2: ethernet-phy@2 { 35 reg = <0x2>; 36 compatible = "ethernet-phy-ieee802.3-c45"; 37 }; 38 39 slot1_sxgmii3: ethernet-phy@3 { 40 reg = <0x3>; 41 compatible = "ethernet-phy-ieee802.3-c45"; 42 }; 43 }; 44 }; 45 46 fragment@1 { 47 target = <&mscc_felix_ports>; 48 49 __overlay__ { 50 port@0 { 51 status = "okay"; 52 phy-handle = <&slot1_sxgmii0>; 53 phy-mode = "2500base-x"; 54 }; 55 56 port@1 { 57 status = "okay"; 58 phy-handle = <&slot1_sxgmii1>; 59 phy-mode = "2500base-x"; 60 }; 61 62 port@2 { 63 status = "okay"; 64 phy-handle = <&slot1_sxgmii2>; 65 phy-mode = "2500base-x"; 66 }; 67 68 port@3 { 69 status = "okay"; 70 phy-handle = <&slot1_sxgmii3>; 71 phy-mode = "2500base-x"; 72 }; 73 }; 74 }; 75 76 fragment@2 { 77 target = <&mscc_felix>; 78 __overlay__ { 79 status = "okay"; 80 }; 81 }; 82}; 83