1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 nand = &gpmi; 17 ssi0 = &ssi1; 18 usb0 = &usbh1; 19 usb1 = &usbotg; 20 }; 21 22 chosen { 23 bootargs = "console=ttymxc1,115200"; 24 }; 25 26 backlight { 27 compatible = "pwm-backlight"; 28 pwms = <&pwm4 0 5000000>; 29 brightness-levels = <0 4 8 16 32 64 128 255>; 30 default-brightness-level = <7>; 31 }; 32 33 gpio-keys { 34 compatible = "gpio-keys"; 35 36 user-pb { 37 label = "user_pb"; 38 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 39 linux,code = <BTN_0>; 40 }; 41 42 user-pb1x { 43 label = "user_pb1x"; 44 linux,code = <BTN_1>; 45 interrupt-parent = <&gsc>; 46 interrupts = <0>; 47 }; 48 49 key-erased { 50 label = "key-erased"; 51 linux,code = <BTN_2>; 52 interrupt-parent = <&gsc>; 53 interrupts = <1>; 54 }; 55 56 eeprom-wp { 57 label = "eeprom_wp"; 58 linux,code = <BTN_3>; 59 interrupt-parent = <&gsc>; 60 interrupts = <2>; 61 }; 62 63 tamper { 64 label = "tamper"; 65 linux,code = <BTN_4>; 66 interrupt-parent = <&gsc>; 67 interrupts = <5>; 68 }; 69 70 switch-hold { 71 label = "switch_hold"; 72 linux,code = <BTN_5>; 73 interrupt-parent = <&gsc>; 74 interrupts = <7>; 75 }; 76 }; 77 78 leds { 79 compatible = "gpio-leds"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_gpio_leds>; 82 83 led0: led-user1 { 84 label = "user1"; 85 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 86 default-state = "on"; 87 linux,default-trigger = "heartbeat"; 88 }; 89 90 led1: led-user2 { 91 label = "user2"; 92 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 93 default-state = "off"; 94 }; 95 96 led2: led-user3 { 97 label = "user3"; 98 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 99 default-state = "off"; 100 }; 101 }; 102 103 memory@10000000 { 104 device_type = "memory"; 105 reg = <0x10000000 0x40000000>; 106 }; 107 108 pps { 109 compatible = "pps-gpio"; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_pps>; 112 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 113 status = "okay"; 114 }; 115 116 reg_1p0v: regulator-1p0v { 117 compatible = "regulator-fixed"; 118 regulator-name = "1P0V"; 119 regulator-min-microvolt = <1000000>; 120 regulator-max-microvolt = <1000000>; 121 regulator-always-on; 122 }; 123 124 reg_3p3v: regulator-3p3v { 125 compatible = "regulator-fixed"; 126 regulator-name = "3P3V"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 regulator-always-on; 130 }; 131 132 reg_can1_stby: regulator-can1-stby { 133 compatible = "regulator-fixed"; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_reg_can1>; 136 regulator-name = "can1_stby"; 137 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 138 regulator-min-microvolt = <3300000>; 139 regulator-max-microvolt = <3300000>; 140 }; 141 142 reg_usb_h1_vbus: regulator-usb-h1-vbus { 143 compatible = "regulator-fixed"; 144 regulator-name = "usb_h1_vbus"; 145 regulator-min-microvolt = <5000000>; 146 regulator-max-microvolt = <5000000>; 147 regulator-always-on; 148 }; 149 150 reg_usb_otg_vbus: regulator-usb-otg-vbus { 151 compatible = "regulator-fixed"; 152 regulator-name = "usb_otg_vbus"; 153 regulator-min-microvolt = <5000000>; 154 regulator-max-microvolt = <5000000>; 155 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 156 enable-active-high; 157 }; 158 159 sound { 160 compatible = "fsl,imx6q-ventana-sgtl5000", 161 "fsl,imx-audio-sgtl5000"; 162 model = "sgtl5000-audio"; 163 ssi-controller = <&ssi1>; 164 audio-codec = <&codec>; 165 audio-routing = 166 "MIC_IN", "Mic Jack", 167 "Mic Jack", "Mic Bias", 168 "Headphone Jack", "HP_OUT"; 169 mux-int-port = <1>; 170 mux-ext-port = <4>; 171 }; 172}; 173 174&audmux { 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_audmux>; 177 status = "okay"; 178}; 179 180&can1 { 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_flexcan1>; 183 xceiver-supply = <®_can1_stby>; 184 status = "okay"; 185}; 186 187&clks { 188 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 189 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 190 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 191 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 192}; 193 194&fec { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_enet>; 197 phy-mode = "rgmii-id"; 198 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 199 status = "okay"; 200}; 201 202&gpmi { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_gpmi_nand>; 205 status = "okay"; 206}; 207 208&hdmi { 209 ddc-i2c-bus = <&i2c3>; 210 status = "okay"; 211}; 212 213&i2c1 { 214 clock-frequency = <100000>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_i2c1>; 217 status = "okay"; 218 219 gsc: gsc@20 { 220 compatible = "gw,gsc"; 221 reg = <0x20>; 222 interrupt-parent = <&gpio1>; 223 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 224 interrupt-controller; 225 #interrupt-cells = <1>; 226 #size-cells = <0>; 227 228 adc { 229 compatible = "gw,gsc-adc"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 233 channel@0 { 234 gw,mode = <0>; 235 reg = <0x00>; 236 label = "temp"; 237 }; 238 239 channel@2 { 240 gw,mode = <1>; 241 reg = <0x02>; 242 label = "vdd_vin"; 243 }; 244 245 channel@5 { 246 gw,mode = <1>; 247 reg = <0x05>; 248 label = "vdd_3p3"; 249 }; 250 251 channel@8 { 252 gw,mode = <1>; 253 reg = <0x08>; 254 label = "vdd_bat"; 255 }; 256 257 channel@b { 258 gw,mode = <1>; 259 reg = <0x0b>; 260 label = "vdd_5p0"; 261 }; 262 263 channel@e { 264 gw,mode = <1>; 265 reg = <0xe>; 266 label = "vdd_arm"; 267 }; 268 269 channel@11 { 270 gw,mode = <1>; 271 reg = <0x11>; 272 label = "vdd_soc"; 273 }; 274 275 channel@14 { 276 gw,mode = <1>; 277 reg = <0x14>; 278 label = "vdd_3p0"; 279 }; 280 281 channel@17 { 282 gw,mode = <1>; 283 reg = <0x17>; 284 label = "vdd_1p5"; 285 }; 286 287 channel@1d { 288 gw,mode = <1>; 289 reg = <0x1d>; 290 label = "vdd_1p8"; 291 }; 292 293 channel@20 { 294 gw,mode = <1>; 295 reg = <0x20>; 296 label = "vdd_1p0"; 297 }; 298 299 channel@23 { 300 gw,mode = <1>; 301 reg = <0x23>; 302 label = "vdd_2p5"; 303 }; 304 305 channel@26 { 306 gw,mode = <1>; 307 reg = <0x26>; 308 label = "vdd_gps"; 309 }; 310 311 channel@29 { 312 gw,mode = <1>; 313 reg = <0x29>; 314 label = "vdd_an1"; 315 }; 316 }; 317 }; 318 319 gsc_gpio: gpio@23 { 320 compatible = "nxp,pca9555"; 321 reg = <0x23>; 322 gpio-controller; 323 #gpio-cells = <2>; 324 interrupt-parent = <&gsc>; 325 interrupts = <4>; 326 }; 327 328 eeprom1: eeprom@50 { 329 compatible = "atmel,24c02"; 330 reg = <0x50>; 331 pagesize = <16>; 332 }; 333 334 eeprom2: eeprom@51 { 335 compatible = "atmel,24c02"; 336 reg = <0x51>; 337 pagesize = <16>; 338 }; 339 340 eeprom3: eeprom@52 { 341 compatible = "atmel,24c02"; 342 reg = <0x52>; 343 pagesize = <16>; 344 }; 345 346 eeprom4: eeprom@53 { 347 compatible = "atmel,24c02"; 348 reg = <0x53>; 349 pagesize = <16>; 350 }; 351 352 rtc: ds1672@68 { 353 compatible = "dallas,ds1672"; 354 reg = <0x68>; 355 }; 356}; 357 358&i2c2 { 359 clock-frequency = <100000>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_i2c2>; 362 status = "okay"; 363 364 ltc3676: pmic@3c { 365 compatible = "lltc,ltc3676"; 366 reg = <0x3c>; 367 interrupt-parent = <&gpio1>; 368 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 369 370 regulators { 371 /* VDD_SOC (1+R1/R2 = 1.635) */ 372 reg_vdd_soc: sw1 { 373 regulator-name = "vddsoc"; 374 regulator-min-microvolt = <674400>; 375 regulator-max-microvolt = <1308000>; 376 lltc,fb-voltage-divider = <127000 200000>; 377 regulator-ramp-delay = <7000>; 378 regulator-boot-on; 379 regulator-always-on; 380 }; 381 382 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 383 reg_1p8v: sw2 { 384 regulator-name = "vdd1p8"; 385 regulator-min-microvolt = <1033310>; 386 regulator-max-microvolt = <2004000>; 387 lltc,fb-voltage-divider = <301000 200000>; 388 regulator-ramp-delay = <7000>; 389 regulator-boot-on; 390 regulator-always-on; 391 }; 392 393 /* VDD_ARM (1+R1/R2 = 1.635) */ 394 reg_vdd_arm: sw3 { 395 regulator-name = "vddarm"; 396 regulator-min-microvolt = <674400>; 397 regulator-max-microvolt = <1308000>; 398 lltc,fb-voltage-divider = <127000 200000>; 399 regulator-ramp-delay = <7000>; 400 regulator-boot-on; 401 regulator-always-on; 402 }; 403 404 /* VDD_DDR (1+R1/R2 = 2.105) */ 405 reg_vdd_ddr: sw4 { 406 regulator-name = "vddddr"; 407 regulator-min-microvolt = <868310>; 408 regulator-max-microvolt = <1684000>; 409 lltc,fb-voltage-divider = <221000 200000>; 410 regulator-ramp-delay = <7000>; 411 regulator-boot-on; 412 regulator-always-on; 413 }; 414 415 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 416 reg_2p5v: ldo2 { 417 regulator-name = "vdd2p5"; 418 regulator-min-microvolt = <2490375>; 419 regulator-max-microvolt = <2490375>; 420 lltc,fb-voltage-divider = <487000 200000>; 421 regulator-boot-on; 422 regulator-always-on; 423 }; 424 425 /* VDD_AUD_1P8: Audio codec */ 426 reg_aud_1p8v: ldo3 { 427 regulator-name = "vdd1p8a"; 428 regulator-min-microvolt = <1800000>; 429 regulator-max-microvolt = <1800000>; 430 regulator-boot-on; 431 }; 432 433 /* VDD_HIGH (1+R1/R2 = 4.17) */ 434 reg_3p0v: ldo4 { 435 regulator-name = "vdd3p0"; 436 regulator-min-microvolt = <3023250>; 437 regulator-max-microvolt = <3023250>; 438 lltc,fb-voltage-divider = <634000 200000>; 439 regulator-boot-on; 440 regulator-always-on; 441 }; 442 }; 443 }; 444}; 445 446&i2c3 { 447 clock-frequency = <100000>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_i2c3>; 450 status = "okay"; 451 452 codec: sgtl5000@a { 453 compatible = "fsl,sgtl5000"; 454 reg = <0x0a>; 455 #sound-dai-cells = <0>; 456 clocks = <&clks IMX6QDL_CLK_CKO>; 457 VDDA-supply = <®_1p8v>; 458 VDDIO-supply = <®_3p3v>; 459 }; 460 461 touchscreen: egalax_ts@4 { 462 compatible = "eeti,egalax_ts"; 463 reg = <0x04>; 464 interrupt-parent = <&gpio1>; 465 interrupts = <11 2>; 466 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 467 }; 468 469 accel@1e { 470 compatible = "nxp,fxos8700"; 471 reg = <0x1e>; 472 }; 473}; 474 475&ldb { 476 status = "okay"; 477 478 lvds-channel@0 { 479 fsl,data-mapping = "spwg"; 480 fsl,data-width = <18>; 481 status = "okay"; 482 483 display-timings { 484 native-mode = <&timing0>; 485 timing0: hsd100pxn1 { 486 clock-frequency = <65000000>; 487 hactive = <1024>; 488 vactive = <768>; 489 hback-porch = <220>; 490 hfront-porch = <40>; 491 vback-porch = <21>; 492 vfront-porch = <7>; 493 hsync-len = <60>; 494 vsync-len = <10>; 495 }; 496 }; 497 }; 498}; 499 500&pcie { 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pinctrl_pcie>; 503 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 504 status = "okay"; 505}; 506 507&pwm2 { 508 pinctrl-names = "default"; 509 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 510 status = "disabled"; 511}; 512 513&pwm3 { 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 516 status = "disabled"; 517}; 518 519&pwm4 { 520 #pwm-cells = <2>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pinctrl_pwm4>; 523 status = "okay"; 524}; 525 526&ssi1 { 527 status = "okay"; 528}; 529 530&uart1 { 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_uart1>; 533 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 534 status = "okay"; 535}; 536 537&uart2 { 538 pinctrl-names = "default"; 539 pinctrl-0 = <&pinctrl_uart2>; 540 status = "okay"; 541}; 542 543&uart5 { 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_uart5>; 546 status = "okay"; 547}; 548 549&usbotg { 550 vbus-supply = <®_usb_otg_vbus>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_usbotg>; 553 disable-over-current; 554 status = "okay"; 555}; 556 557&usbh1 { 558 vbus-supply = <®_usb_h1_vbus>; 559 status = "okay"; 560}; 561 562&usdhc3 { 563 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 564 pinctrl-0 = <&pinctrl_usdhc3>; 565 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 566 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 567 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 568 vmmc-supply = <®_3p3v>; 569 no-1-8-v; /* firmware will remove if board revision supports */ 570 status = "okay"; 571}; 572 573&wdog1 { 574 pinctrl-names = "default"; 575 pinctrl-0 = <&pinctrl_wdog>; 576 fsl,ext-reset-output; 577}; 578 579&iomuxc { 580 pinctrl_audmux: audmuxgrp { 581 fsl,pins = < 582 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 583 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 584 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 585 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 586 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 587 >; 588 }; 589 590 pinctrl_enet: enetgrp { 591 fsl,pins = < 592 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 593 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 594 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 595 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 596 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 597 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 598 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 599 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 600 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 601 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 602 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 603 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 604 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 605 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 606 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 607 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 608 >; 609 }; 610 611 pinctrl_flexcan1: flexcan1grp { 612 fsl,pins = < 613 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 614 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 615 >; 616 }; 617 618 pinctrl_gpio_leds: gpioledsgrp { 619 fsl,pins = < 620 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 621 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 622 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 623 >; 624 }; 625 626 pinctrl_gpmi_nand: gpminandgrp { 627 fsl,pins = < 628 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 629 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 630 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 631 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 632 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 633 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 634 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 635 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 636 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 637 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 638 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 639 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 640 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 641 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 642 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 643 >; 644 }; 645 646 pinctrl_i2c1: i2c1grp { 647 fsl,pins = < 648 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 649 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 650 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 651 >; 652 }; 653 654 pinctrl_i2c2: i2c2grp { 655 fsl,pins = < 656 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 657 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 658 >; 659 }; 660 661 pinctrl_i2c3: i2c3grp { 662 fsl,pins = < 663 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 664 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 665 >; 666 }; 667 668 pinctrl_pcie: pciegrp { 669 fsl,pins = < 670 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 671 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 672 >; 673 }; 674 675 pinctrl_pmic: pmicgrp { 676 fsl,pins = < 677 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 678 >; 679 }; 680 681 pinctrl_pps: ppsgrp { 682 fsl,pins = < 683 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 684 >; 685 }; 686 687 pinctrl_pwm2: pwm2grp { 688 fsl,pins = < 689 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 690 >; 691 }; 692 693 pinctrl_pwm3: pwm3grp { 694 fsl,pins = < 695 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 696 >; 697 }; 698 699 pinctrl_pwm4: pwm4grp { 700 fsl,pins = < 701 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 702 >; 703 }; 704 705 pinctrl_reg_can1: regcan1grp { 706 fsl,pins = < 707 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 708 >; 709 }; 710 711 pinctrl_uart1: uart1grp { 712 fsl,pins = < 713 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 714 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 715 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 716 >; 717 }; 718 719 pinctrl_uart2: uart2grp { 720 fsl,pins = < 721 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 722 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 723 >; 724 }; 725 726 pinctrl_uart5: uart5grp { 727 fsl,pins = < 728 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 729 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 730 >; 731 }; 732 733 pinctrl_usbotg: usbotggrp { 734 fsl,pins = < 735 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 736 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 737 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 738 >; 739 }; 740 741 pinctrl_usdhc3: usdhc3grp { 742 fsl,pins = < 743 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 744 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 745 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 746 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 747 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 748 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 749 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 750 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 751 >; 752 }; 753 754 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 755 fsl,pins = < 756 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 757 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 758 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 759 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 760 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 761 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 762 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 763 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 764 >; 765 }; 766 767 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 768 fsl,pins = < 769 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 770 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 771 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 772 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 773 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 774 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 775 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 776 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 777 >; 778 }; 779 780 pinctrl_wdog: wdoggrp { 781 fsl,pins = < 782 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 783 >; 784 }; 785}; 786