xref: /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/imx27-phytec-phycore-som.dtsi (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Sascha Hauer, Pengutronix
4 */
5
6/dts-v1/;
7#include "imx27.dtsi"
8
9/ {
10	model = "Phytec pcm038";
11	compatible = "phytec,imx27-pcm038", "fsl,imx27";
12
13	memory@a0000000 {
14		device_type = "memory";
15		reg = <0xa0000000 0x08000000>;
16	};
17
18	reg_3v3: regulator-0 {
19		compatible = "regulator-fixed";
20		regulator-name = "3V3";
21		regulator-min-microvolt = <3300000>;
22		regulator-max-microvolt = <3300000>;
23	};
24
25	reg_5v0: regulator-1 {
26		compatible = "regulator-fixed";
27		regulator-name = "5V0";
28		regulator-min-microvolt = <5000000>;
29		regulator-max-microvolt = <5000000>;
30	};
31
32
33	usbphy0: usbphy {
34		compatible = "usb-nop-xceiv";
35		vcc-supply = <&sw3_reg>;
36		clocks = <&clks IMX27_CLK_DUMMY>;
37		clock-names = "main_clk";
38		#phy-cells = <0>;
39	};
40};
41
42&audmux {
43	status = "okay";
44
45	/* SSI0 <=> PINS_4 (MC13783 Audio) */
46	mux-ssi0 {
47		fsl,audmux-port = <0>;
48		fsl,port-config = <0xcb205000>;
49	};
50
51	mux-pins4 {
52		fsl,audmux-port = <2>;
53		fsl,port-config = <0x00001000>;
54	};
55};
56
57&cspi1 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&pinctrl_cspi1>;
60	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
61	status = "okay";
62
63	pmic: mc13783@0 {
64		compatible = "fsl,mc13783";
65		pinctrl-names = "default";
66		pinctrl-0 = <&pinctrl_pmic>;
67		reg = <0>;
68		spi-cs-high;
69		spi-max-frequency = <20000000>;
70		interrupt-parent = <&gpio2>;
71		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
72		fsl,mc13xxx-uses-adc;
73		fsl,mc13xxx-uses-rtc;
74
75		pmicleds: leds {
76			#address-cells = <1>;
77			#size-cells = <0>;
78			led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
79		};
80
81		regulators {
82			/* SW1A and SW1B joined operation */
83			sw1_reg: sw1a {
84				regulator-min-microvolt = <1200000>;
85				regulator-max-microvolt = <1520000>;
86				regulator-always-on;
87				regulator-boot-on;
88			};
89
90			/* SW2A and SW2B joined operation */
91			sw2_reg: sw2a {
92				regulator-min-microvolt = <1800000>;
93				regulator-max-microvolt = <1800000>;
94				regulator-always-on;
95				regulator-boot-on;
96			};
97
98			sw3_reg: sw3 {
99				regulator-min-microvolt = <5000000>;
100				regulator-max-microvolt = <5000000>;
101				regulator-always-on;
102				regulator-boot-on;
103			};
104
105			vaudio_reg: vaudio {
106				regulator-always-on;
107				regulator-boot-on;
108			};
109
110			violo_reg: violo {
111				regulator-min-microvolt = <1800000>;
112				regulator-max-microvolt = <1800000>;
113				regulator-always-on;
114				regulator-boot-on;
115			};
116
117			viohi_reg: viohi {
118				regulator-always-on;
119				regulator-boot-on;
120			};
121
122			vgen_reg: vgen {
123				regulator-min-microvolt = <1500000>;
124				regulator-max-microvolt = <1500000>;
125				regulator-always-on;
126				regulator-boot-on;
127			};
128
129			vcam_reg: vcam {
130				regulator-min-microvolt = <2800000>;
131				regulator-max-microvolt = <2800000>;
132			};
133
134			vrf1_reg: vrf1 {
135				regulator-min-microvolt = <2775000>;
136				regulator-max-microvolt = <2775000>;
137				regulator-always-on;
138				regulator-boot-on;
139			};
140
141			vrf2_reg: vrf2 {
142				regulator-min-microvolt = <2775000>;
143				regulator-max-microvolt = <2775000>;
144				regulator-always-on;
145				regulator-boot-on;
146			};
147
148			vmmc1_reg: vmmc1 {
149				regulator-min-microvolt = <1600000>;
150				regulator-max-microvolt = <3000000>;
151			};
152
153			gpo1_reg: gpo1 { };
154
155			pwgt1spi_reg: pwgt1spi {
156				regulator-always-on;
157			};
158		};
159	};
160};
161
162&fec {
163	phy-mode = "mii";
164	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
165	phy-supply = <&reg_3v3>;
166	pinctrl-names = "default";
167	pinctrl-0 = <&pinctrl_fec1>;
168	status = "okay";
169};
170
171&i2c2 {
172	clock-frequency = <400000>;
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_i2c2>;
175	status = "okay";
176
177	eeprom@52 {
178		compatible = "atmel,24c32";
179		pagesize = <32>;
180		reg = <0x52>;
181	};
182
183	rtc@51 {
184		compatible = "nxp,pcf8563";
185		reg = <0x51>;
186	};
187
188	lm75@4a {
189		compatible = "national,lm75";
190		reg = <0x4a>;
191	};
192};
193
194&iomuxc {
195	imx27_phycore_som {
196		pinctrl_cspi1: cspi1grp {
197			fsl,pins = <
198				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
199				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
200				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
201				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
202			>;
203		};
204
205		pinctrl_fec1: fec1grp {
206			fsl,pins = <
207				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
208				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
209				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
210				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
211				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
212				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
213				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
214				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
215				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
216				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
217				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
218				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
219				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
220				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
221				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
222				MX27_PAD_ATA_DATA13__FEC_COL 0x0
223				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
224				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
225				MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
226			>;
227		};
228
229		pinctrl_i2c2: i2c2grp {
230			fsl,pins = <
231				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
232				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
233			>;
234		};
235
236		pinctrl_nfc: nfcgrp {
237			fsl,pins = <
238				MX27_PAD_NFRB__NFRB 0x0
239				MX27_PAD_NFCLE__NFCLE 0x0
240				MX27_PAD_NFWP_B__NFWP_B 0x0
241				MX27_PAD_NFCE_B__NFCE_B 0x0
242				MX27_PAD_NFALE__NFALE 0x0
243				MX27_PAD_NFRE_B__NFRE_B 0x0
244				MX27_PAD_NFWE_B__NFWE_B 0x0
245			>;
246		};
247
248		pinctrl_pmic: pmicgrp {
249			fsl,pins = <
250				MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
251			>;
252		};
253
254		pinctrl_ssi1: ssi1grp {
255			fsl,pins = <
256				MX27_PAD_SSI1_FS__SSI1_FS 0x0
257				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
258				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
259				MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
260			>;
261		};
262
263		pinctrl_usbotg: usbotggrp {
264			fsl,pins = <
265				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
266				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
267				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
268				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
269				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
270				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
271				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
272				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
273				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
274				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
275				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
276				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
277			>;
278		};
279	};
280};
281
282&nfc {
283	pinctrl-names = "default";
284	pinctrl-0 = <&pinctrl_nfc>;
285	nand-bus-width = <8>;
286	nand-ecc-mode = "hw";
287	nand-on-flash-bbt;
288	status = "okay";
289};
290
291&ssi1 {
292	pinctrl-names = "default";
293	pinctrl-0 = <&pinctrl_ssi1>;
294	status = "okay";
295};
296
297&usbotg {
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_usbotg>;
300	dr_mode = "otg";
301	phy_type = "ulpi";
302	fsl,usbphy = <&usbphy0>;
303	vbus-supply = <&sw3_reg>;
304	disable-over-current;
305	status = "okay";
306};
307
308&weim {
309	status = "okay";
310
311	nor: flash@0,0 {
312		compatible = "cfi-flash";
313		reg = <0 0x00000000 0x02000000>;
314		bank-width = <2>;
315		linux,mtd-name = "physmap-flash.0";
316		fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
317		#address-cells = <1>;
318		#size-cells = <1>;
319	};
320
321	sram: sram@1,0 {
322		compatible = "mtd-ram";
323		reg = <1 0x00000000 0x00800000>;
324		bank-width = <2>;
325		linux,mtd-name = "mtd-ram.0";
326		fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
327		#address-cells = <1>;
328		#size-cells = <1>;
329	};
330};
331