1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC 4 * 5 * Copyright (C) 2012 Atmel, 6 * 2012 Hong Xu <hong.xu@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/pinctrl/at91.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/clock/at91.h> 14#include <dt-bindings/mfd/at91-usart.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 model = "Atmel AT91SAM9N12 SoC"; 20 compatible = "atmel,at91sam9n12"; 21 interrupt-parent = <&aic>; 22 23 aliases { 24 serial0 = &dbgu; 25 serial1 = &usart0; 26 serial2 = &usart1; 27 serial3 = &usart2; 28 serial4 = &usart3; 29 gpio0 = &pioA; 30 gpio1 = &pioB; 31 gpio2 = &pioC; 32 gpio3 = &pioD; 33 tcb0 = &tcb0; 34 tcb1 = &tcb1; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 ssc0 = &ssc0; 38 pwm0 = &pwm0; 39 }; 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu@0 { 45 compatible = "arm,arm926ej-s"; 46 device_type = "cpu"; 47 reg = <0>; 48 }; 49 }; 50 51 memory@20000000 { 52 device_type = "memory"; 53 reg = <0x20000000 0x10000000>; 54 }; 55 56 clocks { 57 slow_xtal: slow_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <0>; 61 }; 62 63 main_xtal: main_xtal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 }; 69 70 sram: sram@300000 { 71 compatible = "mmio-sram"; 72 reg = <0x00300000 0x8000>; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges = <0 0x00300000 0x8000>; 76 }; 77 78 ahb { 79 compatible = "simple-bus"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges; 83 84 apb { 85 compatible = "simple-bus"; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges; 89 90 aic: interrupt-controller@fffff000 { 91 #interrupt-cells = <3>; 92 compatible = "atmel,at91rm9200-aic"; 93 interrupt-controller; 94 reg = <0xfffff000 0x200>; 95 atmel,external-irqs = <31>; 96 }; 97 98 matrix: matrix@ffffde00 { 99 compatible = "atmel,at91sam9n12-matrix", "syscon"; 100 reg = <0xffffde00 0x100>; 101 }; 102 103 pmecc: ecc-engine@ffffe000 { 104 compatible = "atmel,at91sam9g45-pmecc"; 105 reg = <0xffffe000 0x600>, 106 <0xffffe600 0x200>; 107 }; 108 109 ramc0: ramc@ffffe800 { 110 compatible = "atmel,at91sam9g45-ddramc"; 111 reg = <0xffffe800 0x200>; 112 clocks = <&pmc PMC_TYPE_SYSTEM 2>; 113 clock-names = "ddrck"; 114 }; 115 116 smc: smc@ffffea00 { 117 compatible = "atmel,at91sam9260-smc", "syscon"; 118 reg = <0xffffea00 0x200>; 119 }; 120 121 pmc: clock-controller@fffffc00 { 122 compatible = "atmel,at91sam9n12-pmc", "syscon"; 123 reg = <0xfffffc00 0x200>; 124 #clock-cells = <2>; 125 clocks = <&clk32k>, <&main_xtal>; 126 clock-names = "slow_clk", "main_xtal"; 127 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 128 }; 129 130 reset-controller@fffffe00 { 131 compatible = "atmel,at91sam9g45-rstc"; 132 reg = <0xfffffe00 0x10>; 133 clocks = <&clk32k>; 134 }; 135 136 pit: timer@fffffe30 { 137 compatible = "atmel,at91sam9260-pit"; 138 reg = <0xfffffe30 0xf>; 139 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 140 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 141 }; 142 143 poweroff@fffffe10 { 144 compatible = "atmel,at91sam9x5-shdwc"; 145 reg = <0xfffffe10 0x10>; 146 clocks = <&clk32k>; 147 }; 148 149 clk32k: clock-controller@fffffe50 { 150 compatible = "atmel,at91sam9x5-sckc"; 151 reg = <0xfffffe50 0x4>; 152 clocks = <&slow_xtal>; 153 #clock-cells = <0>; 154 }; 155 156 mmc0: mmc@f0008000 { 157 compatible = "atmel,hsmci"; 158 reg = <0xf0008000 0x600>; 159 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 160 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 161 dma-names = "rxtx"; 162 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 163 clock-names = "mci_clk"; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 status = "disabled"; 167 }; 168 169 tcb0: timer@f8008000 { 170 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 reg = <0xf8008000 0x100>; 174 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 175 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; 176 clock-names = "t0_clk", "slow_clk"; 177 }; 178 179 tcb1: timer@f800c000 { 180 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <0xf800c000 0x100>; 184 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 185 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; 186 clock-names = "t0_clk", "slow_clk"; 187 }; 188 189 hlcdc: hlcdc@f8038000 { 190 compatible = "atmel,at91sam9n12-hlcdc"; 191 reg = <0xf8038000 0x2000>; 192 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 193 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 194 clock-names = "periph_clk", "sys_clk", "slow_clk"; 195 status = "disabled"; 196 197 hlcdc-display-controller { 198 compatible = "atmel,hlcdc-display-controller"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 port@0 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 reg = <0>; 206 }; 207 }; 208 209 hlcdc_pwm: hlcdc-pwm { 210 compatible = "atmel,hlcdc-pwm"; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_lcd_pwm>; 213 #pwm-cells = <3>; 214 }; 215 }; 216 217 dma: dma-controller@ffffec00 { 218 compatible = "atmel,at91sam9g45-dma"; 219 reg = <0xffffec00 0x200>; 220 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 221 #dma-cells = <2>; 222 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 223 clock-names = "dma_clk"; 224 }; 225 226 pinctrl@fffff400 { 227 #address-cells = <1>; 228 #size-cells = <1>; 229 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 230 ranges = <0xfffff400 0xfffff400 0x800>; 231 232 atmel,mux-mask = < 233 /* A B C */ 234 0xffffffff 0xffe07983 0x00000000 /* pioA */ 235 0x00040000 0x00047e0f 0x00000000 /* pioB */ 236 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ 237 0x003fffff 0x003f8000 0x00000000 /* pioD */ 238 >; 239 240 /* shared pinctrl settings */ 241 dbgu { 242 pinctrl_dbgu: dbgu-0 { 243 atmel,pins = 244 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 245 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 246 }; 247 }; 248 249 lcd { 250 pinctrl_lcd_base: lcd-base-0 { 251 atmel,pins = 252 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ 253 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ 254 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ 255 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ 256 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ 257 }; 258 259 pinctrl_lcd_pwm: lcd-pwm-0 { 260 atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ 261 }; 262 263 pinctrl_lcd_rgb888: lcd-rgb-3 { 264 atmel,pins = 265 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 266 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 267 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 268 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 269 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 270 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 271 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 272 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 273 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 274 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 275 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 276 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 277 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 278 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 279 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 280 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 281 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ 282 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 283 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 284 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 285 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 286 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 287 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 288 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 289 }; 290 }; 291 292 usart0 { 293 pinctrl_usart0: usart0-0 { 294 atmel,pins = 295 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ 296 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ 297 }; 298 299 pinctrl_usart0_rts: usart0_rts-0 { 300 atmel,pins = 301 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ 302 }; 303 304 pinctrl_usart0_cts: usart0_cts-0 { 305 atmel,pins = 306 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ 307 }; 308 }; 309 310 usart1 { 311 pinctrl_usart1: usart1-0 { 312 atmel,pins = 313 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ 314 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ 315 }; 316 }; 317 318 usart2 { 319 pinctrl_usart2: usart2-0 { 320 atmel,pins = 321 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ 322 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ 323 }; 324 325 pinctrl_usart2_rts: usart2_rts-0 { 326 atmel,pins = 327 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 328 }; 329 330 pinctrl_usart2_cts: usart2_cts-0 { 331 atmel,pins = 332 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 333 }; 334 }; 335 336 usart3 { 337 pinctrl_usart3: usart3-0 { 338 atmel,pins = 339 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ 340 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ 341 }; 342 343 pinctrl_usart3_rts: usart3_rts-0 { 344 atmel,pins = 345 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ 346 }; 347 348 pinctrl_usart3_cts: usart3_cts-0 { 349 atmel,pins = 350 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ 351 }; 352 }; 353 354 uart0 { 355 pinctrl_uart0: uart0-0 { 356 atmel,pins = 357 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ 358 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ 359 }; 360 }; 361 362 uart1 { 363 pinctrl_uart1: uart1-0 { 364 atmel,pins = 365 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE 366 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; 367 }; 368 }; 369 370 nand { 371 pinctrl_nand_rb: nand-rb-0 { 372 atmel,pins = 373 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 374 }; 375 376 pinctrl_nand_cs: nand-cs-0 { 377 atmel,pins = 378 <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 379 }; 380 }; 381 382 mmc0 { 383 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { 384 atmel,pins = 385 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 386 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ 387 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ 388 }; 389 390 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 391 atmel,pins = 392 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ 393 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ 394 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ 395 }; 396 397 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { 398 atmel,pins = 399 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ 400 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ 401 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ 402 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ 403 }; 404 }; 405 406 ssc0 { 407 pinctrl_ssc0_tx: ssc0_tx-0 { 408 atmel,pins = 409 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ 410 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 411 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ 412 }; 413 414 pinctrl_ssc0_rx: ssc0_rx-0 { 415 atmel,pins = 416 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 417 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 418 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 419 }; 420 }; 421 422 spi0 { 423 pinctrl_spi0: spi0-0 { 424 atmel,pins = 425 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ 426 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ 427 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ 428 }; 429 }; 430 431 spi1 { 432 pinctrl_spi1: spi1-0 { 433 atmel,pins = 434 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ 435 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ 436 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ 437 }; 438 }; 439 440 i2c0 { 441 pinctrl_i2c0: i2c0-0 { 442 atmel,pins = 443 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE 444 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 445 }; 446 }; 447 448 i2c1 { 449 pinctrl_i2c1: i2c1-0 { 450 atmel,pins = 451 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE 452 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; 453 }; 454 }; 455 456 tcb0 { 457 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 458 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; 459 }; 460 461 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 462 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 463 }; 464 465 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 466 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 467 }; 468 469 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 470 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 471 }; 472 473 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 474 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 475 }; 476 477 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 478 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 479 }; 480 481 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 482 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 483 }; 484 485 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 486 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 487 }; 488 489 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 490 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 491 }; 492 }; 493 494 tcb1 { 495 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 496 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; 497 }; 498 499 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 500 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; 501 }; 502 503 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 504 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; 505 }; 506 507 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 508 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; 509 }; 510 511 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 512 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; 513 }; 514 515 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 516 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; 517 }; 518 519 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 520 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; 521 }; 522 523 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 524 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; 525 }; 526 527 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 528 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; 529 }; 530 }; 531 532 pioA: gpio@fffff400 { 533 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 534 reg = <0xfffff400 0x200>; 535 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 536 #gpio-cells = <2>; 537 gpio-controller; 538 interrupt-controller; 539 #interrupt-cells = <2>; 540 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 541 }; 542 543 pioB: gpio@fffff600 { 544 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 545 reg = <0xfffff600 0x200>; 546 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 547 #gpio-cells = <2>; 548 gpio-controller; 549 interrupt-controller; 550 #interrupt-cells = <2>; 551 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 552 }; 553 554 pioC: gpio@fffff800 { 555 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 556 reg = <0xfffff800 0x200>; 557 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 558 #gpio-cells = <2>; 559 gpio-controller; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 563 }; 564 565 pioD: gpio@fffffa00 { 566 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 567 reg = <0xfffffa00 0x200>; 568 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 569 #gpio-cells = <2>; 570 gpio-controller; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 574 }; 575 }; 576 577 dbgu: serial@fffff200 { 578 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 579 reg = <0xfffff200 0x200>; 580 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 581 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&pinctrl_dbgu>; 584 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 585 clock-names = "usart"; 586 status = "disabled"; 587 }; 588 589 ssc0: ssc@f0010000 { 590 compatible = "atmel,at91sam9g45-ssc"; 591 reg = <0xf0010000 0x4000>; 592 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 593 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, 594 <&dma 0 AT91_DMA_CFG_PER_ID(22)>; 595 dma-names = "tx", "rx"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 598 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 599 clock-names = "pclk"; 600 status = "disabled"; 601 }; 602 603 usart0: serial@f801c000 { 604 compatible = "atmel,at91sam9260-usart"; 605 reg = <0xf801c000 0x4000>; 606 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 607 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&pinctrl_usart0>; 610 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 611 clock-names = "usart"; 612 status = "disabled"; 613 }; 614 615 usart1: serial@f8020000 { 616 compatible = "atmel,at91sam9260-usart"; 617 reg = <0xf8020000 0x4000>; 618 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 619 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&pinctrl_usart1>; 622 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 623 clock-names = "usart"; 624 status = "disabled"; 625 }; 626 627 usart2: serial@f8024000 { 628 compatible = "atmel,at91sam9260-usart"; 629 reg = <0xf8024000 0x4000>; 630 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 631 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_usart2>; 634 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 635 clock-names = "usart"; 636 status = "disabled"; 637 }; 638 639 usart3: serial@f8028000 { 640 compatible = "atmel,at91sam9260-usart"; 641 reg = <0xf8028000 0x4000>; 642 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 643 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_usart3>; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 647 clock-names = "usart"; 648 status = "disabled"; 649 }; 650 651 i2c0: i2c@f8010000 { 652 compatible = "atmel,at91sam9x5-i2c"; 653 reg = <0xf8010000 0x100>; 654 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; 655 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, 656 <&dma 1 AT91_DMA_CFG_PER_ID(14)>; 657 dma-names = "tx", "rx"; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_i2c0>; 662 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 663 status = "disabled"; 664 }; 665 666 i2c1: i2c@f8014000 { 667 compatible = "atmel,at91sam9x5-i2c"; 668 reg = <0xf8014000 0x100>; 669 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; 670 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, 671 <&dma 1 AT91_DMA_CFG_PER_ID(16)>; 672 dma-names = "tx", "rx"; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&pinctrl_i2c1>; 677 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 678 status = "disabled"; 679 }; 680 681 spi0: spi@f0000000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "atmel,at91rm9200-spi"; 685 reg = <0xf0000000 0x100>; 686 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 687 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, 688 <&dma 1 AT91_DMA_CFG_PER_ID(2)>; 689 dma-names = "tx", "rx"; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pinctrl_spi0>; 692 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 693 clock-names = "spi_clk"; 694 status = "disabled"; 695 }; 696 697 spi1: spi@f0004000 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 compatible = "atmel,at91rm9200-spi"; 701 reg = <0xf0004000 0x100>; 702 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; 703 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, 704 <&dma 1 AT91_DMA_CFG_PER_ID(4)>; 705 dma-names = "tx", "rx"; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_spi1>; 708 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 709 clock-names = "spi_clk"; 710 status = "disabled"; 711 }; 712 713 watchdog@fffffe40 { 714 compatible = "atmel,at91sam9260-wdt"; 715 reg = <0xfffffe40 0x10>; 716 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 717 clocks = <&clk32k>; 718 atmel,watchdog-type = "hardware"; 719 atmel,reset-type = "all"; 720 atmel,dbg-halt; 721 status = "disabled"; 722 }; 723 724 rtc@fffffeb0 { 725 compatible = "atmel,at91rm9200-rtc"; 726 reg = <0xfffffeb0 0x40>; 727 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 728 clocks = <&clk32k>; 729 status = "disabled"; 730 }; 731 732 pwm0: pwm@f8034000 { 733 compatible = "atmel,at91sam9rl-pwm"; 734 reg = <0xf8034000 0x300>; 735 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 736 #pwm-cells = <3>; 737 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 738 status = "disabled"; 739 }; 740 741 usb1: gadget@f803c000 { 742 compatible = "atmel,at91sam9260-udc"; 743 reg = <0xf803c000 0x4000>; 744 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 745 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; 746 clock-names = "pclk", "hclk"; 747 status = "disabled"; 748 }; 749 }; 750 751 usb0: ohci@500000 { 752 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 753 reg = <0x00500000 0x00100000>; 754 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 755 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 756 clock-names = "ohci_clk", "hclk", "uhpck"; 757 status = "disabled"; 758 }; 759 760 ebi: ebi@10000000 { 761 compatible = "atmel,at91sam9x5-ebi"; 762 #address-cells = <2>; 763 #size-cells = <1>; 764 atmel,smc = <&smc>; 765 atmel,matrix = <&matrix>; 766 reg = <0x10000000 0x60000000>; 767 ranges = <0x0 0x0 0x10000000 0x10000000 768 0x1 0x0 0x20000000 0x10000000 769 0x2 0x0 0x30000000 0x10000000 770 0x3 0x0 0x40000000 0x10000000 771 0x4 0x0 0x50000000 0x10000000 772 0x5 0x0 0x60000000 0x10000000>; 773 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 774 status = "disabled"; 775 776 nand_controller: nand-controller { 777 compatible = "atmel,at91sam9g45-nand-controller"; 778 ecc-engine = <&pmecc>; 779 #address-cells = <2>; 780 #size-cells = <1>; 781 ranges; 782 status = "disabled"; 783 }; 784 }; 785 }; 786 787 i2c-gpio-0 { 788 compatible = "i2c-gpio"; 789 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ 790 &pioA 31 GPIO_ACTIVE_HIGH /* scl */ 791 >; 792 i2c-gpio,sda-open-drain; 793 i2c-gpio,scl-open-drain; 794 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 795 #address-cells = <1>; 796 #size-cells = <0>; 797 status = "disabled"; 798 }; 799}; 800