xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/reset/mediatek,mt6735-infracfg.h (revision 5f62a964e9f8abc6a05d8338273fadd154f0a206)
1*5f62a964SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*5f62a964SEmmanuel Vadot 
3*5f62a964SEmmanuel Vadot #ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
4*5f62a964SEmmanuel Vadot #define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
5*5f62a964SEmmanuel Vadot 
6*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_EMI_REG		0
7*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_DRAMC0_AO		1
8*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_AP_CIRQ_EINT		2
9*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_APXGPT		3
10*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_SCPSYS		4
11*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_KP			5
12*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_PMIC_WRAP		6
13*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_CLDMA_AO_TOP		7
14*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_USBSIF_TOP		8
15*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_EMI			9
16*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_CCIF			10
17*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_DRAMC0		11
18*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_EMI_AO_REG		12
19*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_CCIF_AO		13
20*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_TRNG			14
21*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_SYS_CIRQ		15
22*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_GCE			16
23*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_M4U			17
24*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_CCIF1			18
25*5f62a964SEmmanuel Vadot #define MT6735_INFRA_RST0_CLDMA_TOP_PD		19
26*5f62a964SEmmanuel Vadot 
27*5f62a964SEmmanuel Vadot #endif
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