1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_IMX1_H 7*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_IMX1_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot #define IMX1_CLK_DUMMY 0 10*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CLK32 1 11*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CLK16M_EXT 2 12*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CLK16M 3 13*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CLK32_PREMULT 4 14*c66ec88fSEmmanuel Vadot #define IMX1_CLK_PREM 5 15*c66ec88fSEmmanuel Vadot #define IMX1_CLK_MPLL 6 16*c66ec88fSEmmanuel Vadot #define IMX1_CLK_MPLL_GATE 7 17*c66ec88fSEmmanuel Vadot #define IMX1_CLK_SPLL 8 18*c66ec88fSEmmanuel Vadot #define IMX1_CLK_SPLL_GATE 9 19*c66ec88fSEmmanuel Vadot #define IMX1_CLK_MCU 10 20*c66ec88fSEmmanuel Vadot #define IMX1_CLK_FCLK 11 21*c66ec88fSEmmanuel Vadot #define IMX1_CLK_HCLK 12 22*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CLK48M 13 23*c66ec88fSEmmanuel Vadot #define IMX1_CLK_PER1 14 24*c66ec88fSEmmanuel Vadot #define IMX1_CLK_PER2 15 25*c66ec88fSEmmanuel Vadot #define IMX1_CLK_PER3 16 26*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CLKO 17 27*c66ec88fSEmmanuel Vadot #define IMX1_CLK_UART3_GATE 18 28*c66ec88fSEmmanuel Vadot #define IMX1_CLK_SSI2_GATE 19 29*c66ec88fSEmmanuel Vadot #define IMX1_CLK_BROM_GATE 20 30*c66ec88fSEmmanuel Vadot #define IMX1_CLK_DMA_GATE 21 31*c66ec88fSEmmanuel Vadot #define IMX1_CLK_CSI_GATE 22 32*c66ec88fSEmmanuel Vadot #define IMX1_CLK_MMA_GATE 23 33*c66ec88fSEmmanuel Vadot #define IMX1_CLK_USBD_GATE 24 34*c66ec88fSEmmanuel Vadot #define IMX1_CLK_MAX 25 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadot #endif 37