xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/exynos7885.h (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145)
1e67e8565SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2e67e8565SEmmanuel Vadot /*
3e67e8565SEmmanuel Vadot  * Copyright (c) 2021 Dávid Virág
4e67e8565SEmmanuel Vadot  *
5e67e8565SEmmanuel Vadot  * Device Tree binding constants for Exynos7885 clock controller.
6e67e8565SEmmanuel Vadot  */
7e67e8565SEmmanuel Vadot 
8e67e8565SEmmanuel Vadot #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
9e67e8565SEmmanuel Vadot #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
10e67e8565SEmmanuel Vadot 
11e67e8565SEmmanuel Vadot /* CMU_TOP */
12e67e8565SEmmanuel Vadot #define CLK_FOUT_SHARED0_PLL		1
13e67e8565SEmmanuel Vadot #define CLK_FOUT_SHARED1_PLL		2
14e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED0_DIV2		3
15e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED0_DIV3		4
16e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED0_DIV4		5
17e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED0_DIV5		6
18e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED1_DIV2		7
19e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED1_DIV3		8
20e67e8565SEmmanuel Vadot #define CLK_DOUT_SHARED1_DIV4		9
21e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_BUS		10
22e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_CCI		11
23e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_G3D		12
24e67e8565SEmmanuel Vadot #define CLK_DOUT_CORE_BUS		13
25e67e8565SEmmanuel Vadot #define CLK_DOUT_CORE_CCI		14
26e67e8565SEmmanuel Vadot #define CLK_DOUT_CORE_G3D		15
27e67e8565SEmmanuel Vadot #define CLK_GOUT_CORE_BUS		16
28e67e8565SEmmanuel Vadot #define CLK_GOUT_CORE_CCI		17
29e67e8565SEmmanuel Vadot #define CLK_GOUT_CORE_G3D		18
30e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_BUS		19
31e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_SPI0		20
32e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_SPI1		21
33e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_UART0		22
34e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_UART1		23
35e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_UART2		24
36e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_USI0		25
37e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_USI1		26
38e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_USI2		27
39e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_BUS		28
40e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_SPI0		29
41e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_SPI1		30
42e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_UART0		31
43e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_UART1		32
44e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_UART2		33
45e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_USI0		34
46e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_USI1		35
47e67e8565SEmmanuel Vadot #define CLK_DOUT_PERI_USI2		36
48e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_BUS		37
49e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_SPI0		38
50e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_SPI1		39
51e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_UART0		40
52e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_UART1		41
53e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_UART2		42
54e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_USI0		43
55e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_USI1		44
56e67e8565SEmmanuel Vadot #define CLK_GOUT_PERI_USI2		45
57*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_BUS		46
58*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_MMC_CARD		47
59*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_MMC_EMBD		48
60*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_MMC_SDIO		49
61*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_USB30DRD		50
62*b97ee269SEmmanuel Vadot #define CLK_DOUT_FSYS_BUS		51
63*b97ee269SEmmanuel Vadot #define CLK_DOUT_FSYS_MMC_CARD		52
64*b97ee269SEmmanuel Vadot #define CLK_DOUT_FSYS_MMC_EMBD		53
65*b97ee269SEmmanuel Vadot #define CLK_DOUT_FSYS_MMC_SDIO		54
66*b97ee269SEmmanuel Vadot #define CLK_DOUT_FSYS_USB30DRD		55
67*b97ee269SEmmanuel Vadot #define CLK_GOUT_FSYS_BUS		56
68*b97ee269SEmmanuel Vadot #define CLK_GOUT_FSYS_MMC_CARD		57
69*b97ee269SEmmanuel Vadot #define CLK_GOUT_FSYS_MMC_EMBD		58
70*b97ee269SEmmanuel Vadot #define CLK_GOUT_FSYS_MMC_SDIO		59
71*b97ee269SEmmanuel Vadot #define CLK_GOUT_FSYS_USB30DRD		60
72e67e8565SEmmanuel Vadot 
73e67e8565SEmmanuel Vadot /* CMU_CORE */
74e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_BUS_USER			1
75e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_CCI_USER			2
76e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_G3D_USER			3
77e67e8565SEmmanuel Vadot #define CLK_MOUT_CORE_GIC			4
78e67e8565SEmmanuel Vadot #define CLK_DOUT_CORE_BUSP			5
79e67e8565SEmmanuel Vadot #define CLK_GOUT_CCI_ACLK			6
80e67e8565SEmmanuel Vadot #define CLK_GOUT_GIC400_CLK			7
81*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_D_CORE_ACLK		8
82*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_D_CORE_GCLK		9
83*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_D_CORE_PCLK		10
84*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE	11
85*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12
86*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_P_CORE_PCLK		13
87*b97ee269SEmmanuel Vadot #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14
88e67e8565SEmmanuel Vadot 
89e67e8565SEmmanuel Vadot /* CMU_PERI */
90e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_BUS_USER		1
91e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_SPI0_USER		2
92e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_SPI1_USER		3
93e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_UART0_USER	4
94e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_UART1_USER	5
95e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_UART2_USER	6
96e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_USI0_USER		7
97e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_USI1_USER		8
98e67e8565SEmmanuel Vadot #define CLK_MOUT_PERI_USI2_USER		9
99e67e8565SEmmanuel Vadot #define CLK_GOUT_GPIO_TOP_PCLK		10
100e67e8565SEmmanuel Vadot #define CLK_GOUT_HSI2C0_PCLK		11
101e67e8565SEmmanuel Vadot #define CLK_GOUT_HSI2C1_PCLK		12
102e67e8565SEmmanuel Vadot #define CLK_GOUT_HSI2C2_PCLK		13
103e67e8565SEmmanuel Vadot #define CLK_GOUT_HSI2C3_PCLK		14
104e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C0_PCLK		15
105e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C1_PCLK		16
106e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C2_PCLK		17
107e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C3_PCLK		18
108e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C4_PCLK		19
109e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C5_PCLK		20
110e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C6_PCLK		21
111e67e8565SEmmanuel Vadot #define CLK_GOUT_I2C7_PCLK		22
112e67e8565SEmmanuel Vadot #define CLK_GOUT_PWM_MOTOR_PCLK		23
113e67e8565SEmmanuel Vadot #define CLK_GOUT_SPI0_PCLK		24
114e67e8565SEmmanuel Vadot #define CLK_GOUT_SPI0_EXT_CLK		25
115e67e8565SEmmanuel Vadot #define CLK_GOUT_SPI1_PCLK		26
116e67e8565SEmmanuel Vadot #define CLK_GOUT_SPI1_EXT_CLK		27
117e67e8565SEmmanuel Vadot #define CLK_GOUT_UART0_EXT_UCLK		28
118e67e8565SEmmanuel Vadot #define CLK_GOUT_UART0_PCLK		29
119e67e8565SEmmanuel Vadot #define CLK_GOUT_UART1_EXT_UCLK		30
120e67e8565SEmmanuel Vadot #define CLK_GOUT_UART1_PCLK		31
121e67e8565SEmmanuel Vadot #define CLK_GOUT_UART2_EXT_UCLK		32
122e67e8565SEmmanuel Vadot #define CLK_GOUT_UART2_PCLK		33
123e67e8565SEmmanuel Vadot #define CLK_GOUT_USI0_PCLK		34
124e67e8565SEmmanuel Vadot #define CLK_GOUT_USI0_SCLK		35
125e67e8565SEmmanuel Vadot #define CLK_GOUT_USI1_PCLK		36
126e67e8565SEmmanuel Vadot #define CLK_GOUT_USI1_SCLK		37
127e67e8565SEmmanuel Vadot #define CLK_GOUT_USI2_PCLK		38
128e67e8565SEmmanuel Vadot #define CLK_GOUT_USI2_SCLK		39
129e67e8565SEmmanuel Vadot #define CLK_GOUT_MCT_PCLK		40
130e67e8565SEmmanuel Vadot #define CLK_GOUT_SYSREG_PERI_PCLK	41
131e67e8565SEmmanuel Vadot #define CLK_GOUT_WDT0_PCLK		42
132e67e8565SEmmanuel Vadot #define CLK_GOUT_WDT1_PCLK		43
133e67e8565SEmmanuel Vadot 
134*b97ee269SEmmanuel Vadot /* CMU_FSYS */
135*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_BUS_USER		1
136*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_MMC_CARD_USER	2
137*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_MMC_EMBD_USER	3
138*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_MMC_SDIO_USER	4
139*b97ee269SEmmanuel Vadot #define CLK_MOUT_FSYS_USB30DRD_USER	4
140*b97ee269SEmmanuel Vadot #define CLK_GOUT_MMC_CARD_ACLK		5
141*b97ee269SEmmanuel Vadot #define CLK_GOUT_MMC_CARD_SDCLKIN	6
142*b97ee269SEmmanuel Vadot #define CLK_GOUT_MMC_EMBD_ACLK		7
143*b97ee269SEmmanuel Vadot #define CLK_GOUT_MMC_EMBD_SDCLKIN	8
144*b97ee269SEmmanuel Vadot #define CLK_GOUT_MMC_SDIO_ACLK		9
145*b97ee269SEmmanuel Vadot #define CLK_GOUT_MMC_SDIO_SDCLKIN	10
146*b97ee269SEmmanuel Vadot 
147e67e8565SEmmanuel Vadot #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
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