xref: /freebsd/sys/contrib/device-tree/Bindings/spi/qcom,spi-qup.yaml (revision 84943d6f38e936ac3b7a3947ca26eeb27a39f938) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
8
9maintainers:
10  - Andy Gross <agross@kernel.org>
11  - Bjorn Andersson <bjorn.andersson@linaro.org>
12  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13
14description:
15  The QUP core is an AHB slave that provides a common data path (an output FIFO
16  and an input FIFO) for serial peripheral interface (SPI) mini-core.
17
18  SPI in master mode supports up to 50MHz, up to four chip selects,
19  programmable data path from 4 bits to 32 bits and numerous protocol variants.
20
21allOf:
22  - $ref: /schemas/spi/spi-controller.yaml#
23
24properties:
25  compatible:
26    enum:
27      - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
28      - qcom,spi-qup-v2.1.1 # for 8974 and later
29      - qcom,spi-qup-v2.2.1 # for 8974 v2 and later
30
31  clocks:
32    maxItems: 2
33
34  clock-names:
35    items:
36      - const: core
37      - const: iface
38
39  dmas:
40    maxItems: 2
41
42  dma-names:
43    items:
44      - const: tx
45      - const: rx
46
47  interconnects:
48    maxItems: 1
49
50  interrupts:
51    maxItems: 1
52
53  operating-points-v2: true
54
55  power-domains:
56    maxItems: 1
57
58  reg:
59    maxItems: 1
60
61required:
62  - compatible
63  - clocks
64  - clock-names
65  - interrupts
66  - reg
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
73    #include <dt-bindings/interconnect/qcom,msm8996.h>
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75    #include <dt-bindings/power/qcom-rpmpd.h>
76
77    spi@7575000 {
78        compatible = "qcom,spi-qup-v2.2.1";
79        reg = <0x07575000 0x600>;
80        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
81        clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
82                 <&gcc GCC_BLSP1_AHB_CLK>;
83        clock-names = "core", "iface";
84        pinctrl-names = "default", "sleep";
85        pinctrl-0 = <&blsp1_spi1_default>;
86        pinctrl-1 = <&blsp1_spi1_sleep>;
87        dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
88        dma-names = "tx", "rx";
89        power-domains = <&rpmpd MSM8996_VDDCX>;
90        operating-points-v2 = <&spi_opp_table>;
91        interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
92        #address-cells = <1>;
93        #size-cells = <0>;
94    };
95