1*c66ec88fSEmmanuel VadotNVIDIA Tegra20 SFLASH controller. 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible : should be "nvidia,tegra20-sflash". 5*c66ec88fSEmmanuel Vadot- reg: Should contain SFLASH registers location and length. 6*c66ec88fSEmmanuel Vadot- interrupts: Should contain SFLASH interrupts. 7*c66ec88fSEmmanuel Vadot- clocks : Must contain one entry, for the module clock. 8*c66ec88fSEmmanuel Vadot See ../clocks/clock-bindings.txt for details. 9*c66ec88fSEmmanuel Vadot- resets : Must contain an entry for each entry in reset-names. 10*c66ec88fSEmmanuel Vadot See ../reset/reset.txt for details. 11*c66ec88fSEmmanuel Vadot- reset-names : Must include the following entries: 12*c66ec88fSEmmanuel Vadot - spi 13*c66ec88fSEmmanuel Vadot- dmas : Must contain an entry for each entry in clock-names. 14*c66ec88fSEmmanuel Vadot See ../dma/dma.txt for details. 15*c66ec88fSEmmanuel Vadot- dma-names : Must include the following entries: 16*c66ec88fSEmmanuel Vadot - rx 17*c66ec88fSEmmanuel Vadot - tx 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotRecommended properties: 20*c66ec88fSEmmanuel Vadot- spi-max-frequency: Definition as per 21*c66ec88fSEmmanuel Vadot Documentation/devicetree/bindings/spi/spi-bus.txt 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel VadotExample: 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel Vadotspi@7000c380 { 26*c66ec88fSEmmanuel Vadot compatible = "nvidia,tegra20-sflash"; 27*c66ec88fSEmmanuel Vadot reg = <0x7000c380 0x80>; 28*c66ec88fSEmmanuel Vadot interrupts = <0 39 0x04>; 29*c66ec88fSEmmanuel Vadot spi-max-frequency = <25000000>; 30*c66ec88fSEmmanuel Vadot #address-cells = <1>; 31*c66ec88fSEmmanuel Vadot #size-cells = <0>; 32*c66ec88fSEmmanuel Vadot clocks = <&tegra_car 43>; 33*c66ec88fSEmmanuel Vadot resets = <&tegra_car 43>; 34*c66ec88fSEmmanuel Vadot reset-names = "spi"; 35*c66ec88fSEmmanuel Vadot dmas = <&apbdma 11>, <&apbdma 11>; 36*c66ec88fSEmmanuel Vadot dma-names = "rx", "tx"; 37*c66ec88fSEmmanuel Vadot}; 38