1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: SPI Bus controller for MediaTek ARM SoCs 8 9maintainers: 10 - Leilk Liu <leilk.liu@mediatek.com> 11 12allOf: 13 - $ref: "/schemas/spi/spi-controller.yaml#" 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - mediatek,mt7629-spi 21 - const: mediatek,mt7622-spi 22 - items: 23 - enum: 24 - mediatek,mt8516-spi 25 - const: mediatek,mt2712-spi 26 - items: 27 - enum: 28 - mediatek,mt6779-spi 29 - mediatek,mt8186-spi 30 - mediatek,mt8192-spi 31 - mediatek,mt8195-spi 32 - const: mediatek,mt6765-spi 33 - items: 34 - enum: 35 - mediatek,mt7986-spi-ipm 36 - const: mediatek,spi-ipm 37 - items: 38 - enum: 39 - mediatek,mt2701-spi 40 - mediatek,mt2712-spi 41 - mediatek,mt6589-spi 42 - mediatek,mt6765-spi 43 - mediatek,mt6893-spi 44 - mediatek,mt7622-spi 45 - mediatek,mt8135-spi 46 - mediatek,mt8173-spi 47 - mediatek,mt8183-spi 48 49 reg: 50 maxItems: 1 51 52 interrupts: 53 maxItems: 1 54 55 clocks: 56 items: 57 - description: clock used for the parent clock 58 - description: clock used for the muxes clock 59 - description: clock used for the clock gate 60 61 clock-names: 62 items: 63 - const: parent-clk 64 - const: sel-clk 65 - const: spi-clk 66 67 mediatek,pad-select: 68 $ref: /schemas/types.yaml#/definitions/uint32-array 69 minItems: 1 70 maxItems: 4 71 items: 72 enum: [0, 1, 2, 3] 73 description: 74 specify which pins group(ck/mi/mo/cs) spi controller used. 75 This is an array. 76 77required: 78 - compatible 79 - reg 80 - interrupts 81 - clocks 82 - clock-names 83 - '#address-cells' 84 - '#size-cells' 85 86unevaluatedProperties: false 87 88examples: 89 - | 90 #include <dt-bindings/clock/mt8173-clk.h> 91 #include <dt-bindings/gpio/gpio.h> 92 #include <dt-bindings/interrupt-controller/arm-gic.h> 93 #include <dt-bindings/interrupt-controller/irq.h> 94 95 spi@1100a000 { 96 compatible = "mediatek,mt8173-spi"; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 reg = <0x1100a000 0x1000>; 100 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 101 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 102 <&topckgen CLK_TOP_SPI_SEL>, 103 <&pericfg CLK_PERI_SPI0>; 104 clock-names = "parent-clk", "sel-clk", "spi-clk"; 105 cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; 106 mediatek,pad-select = <1>, <0>; 107 }; 108