1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/{G2L,V2L} USBPHY Control 8 9maintainers: 10 - Biju Das <biju.das.jz@bp.renesas.com> 11 12description: 13 The RZ/G2L USBPHY Control mainly controls reset and power down of the 14 USB/PHY. 15 16properties: 17 compatible: 18 items: 19 - enum: 20 - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five 21 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 22 - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 23 - const: renesas,rzg2l-usbphy-ctrl 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 maxItems: 1 30 31 resets: 32 maxItems: 1 33 34 power-domains: 35 maxItems: 1 36 37 '#reset-cells': 38 const: 1 39 description: | 40 The phandle's argument in the reset specifier is the PHY reset associated 41 with the USB port. 42 0 = Port 1 Phy reset 43 1 = Port 2 Phy reset 44 45required: 46 - compatible 47 - reg 48 - clocks 49 - resets 50 - power-domains 51 - '#reset-cells' 52 53additionalProperties: false 54 55examples: 56 - | 57 #include <dt-bindings/clock/r9a07g044-cpg.h> 58 59 phyrst: usbphy-ctrl@11c40000 { 60 compatible = "renesas,r9a07g044-usbphy-ctrl", 61 "renesas,rzg2l-usbphy-ctrl"; 62 reg = <0x11c40000 0x10000>; 63 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 64 resets = <&cpg R9A07G044_USB_PRESETN>; 65 power-domains = <&cpg>; 66 #reset-cells = <1>; 67 }; 68