1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Microchip IP corePWM controller 9 10maintainers: 11 - Conor Dooley <conor.dooley@microchip.com> 12 13description: | 14 corePWM is an 16 channel pulse width modulator FPGA IP 15 16 https://www.microsemi.com/existing-parts/parts/152118 17 18allOf: 19 - $ref: pwm.yaml# 20 21properties: 22 compatible: 23 items: 24 - const: microchip,corepwm-rtl-v4 25 26 reg: 27 maxItems: 1 28 29 clocks: 30 maxItems: 1 31 32 "#pwm-cells": 33 enum: [2, 3] 34 description: 35 The only flag supported by the controller is PWM_POLARITY_INVERTED. 36 37 microchip,sync-update-mask: 38 description: | 39 Depending on how the IP is instantiated, there are two modes of operation. 40 In synchronous mode, all channels are updated at the beginning of the PWM period, 41 and in asynchronous mode updates happen as the control registers are written. 42 A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous 43 mode is possible for each channel, and is set by the bitstream programmed to the 44 FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that 45 control the duty cycle for channel x have a second "shadow"/buffer reg synthesised. 46 At runtime a bit wide register exposed to APB can be used to toggle on/off 47 synchronised mode for all channels it has been synthesised for. 48 Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents 49 whether synchronous mode is possible for the PWM channel. 50 51 $ref: /schemas/types.yaml#/definitions/uint32 52 default: 0 53 54 microchip,dac-mode-mask: 55 description: | 56 Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates 57 a minimum period pulse train whose High/Low average is that of the chosen duty 58 cycle. This "DAC" will have far better bandwidth and ripple performance than the 59 standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP 60 core, set at instantiation and by the bitstream programmed to the FPGA, determines 61 whether a given channel operates in regular PWM or DAC mode. 62 Each bit corresponds to a PWM channel & represents whether DAC mode is enabled 63 for that channel. 64 65 $ref: /schemas/types.yaml#/definitions/uint32 66 default: 0 67 68required: 69 - compatible 70 - reg 71 - clocks 72 73additionalProperties: false 74 75examples: 76 - | 77 pwm@41000000 { 78 compatible = "microchip,corepwm-rtl-v4"; 79 microchip,sync-update-mask = /bits/ 32 <0>; 80 clocks = <&clkcfg 30>; 81 reg = <0x41000000 0xF0>; 82 #pwm-cells = <2>; 83 }; 84