1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) STMicroelectronics 2019. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: STM32 GPIO and Pin Mux/Config controller 9 10maintainers: 11 - Alexandre TORGUE <alexandre.torgue@foss.st.com> 12 13description: | 14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware 15 controller. It controls the input/output settings on the available pins and 16 also provides ability to multiplex and configure the output of various 17 on-chip controllers onto these pads. 18 19properties: 20 compatible: 21 enum: 22 - st,stm32f429-pinctrl 23 - st,stm32f469-pinctrl 24 - st,stm32f746-pinctrl 25 - st,stm32f769-pinctrl 26 - st,stm32h743-pinctrl 27 - st,stm32mp135-pinctrl 28 - st,stm32mp157-pinctrl 29 - st,stm32mp157-z-pinctrl 30 31 '#address-cells': 32 const: 1 33 '#size-cells': 34 const: 1 35 36 ranges: true 37 pins-are-numbered: true 38 hwlocks: true 39 40 interrupts: 41 maxItems: 1 42 43 st,syscfg: 44 description: Should be phandle/offset/mask 45 - Phandle to the syscon node which includes IRQ mux selection. 46 - The offset of the IRQ mux selection register. 47 - The field mask of IRQ mux, needed if different of 0xf. 48 $ref: "/schemas/types.yaml#/definitions/phandle-array" 49 50 st,package: 51 description: 52 Indicates the SOC package used. 53 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h 54 $ref: /schemas/types.yaml#/definitions/uint32 55 enum: [1, 2, 4, 8] 56 57patternProperties: 58 '^gpio@[0-9a-f]*$': 59 type: object 60 properties: 61 gpio-controller: true 62 '#gpio-cells': 63 const: 2 64 65 reg: 66 maxItems: 1 67 clocks: 68 maxItems: 1 69 reset: 70 minItems: 1 71 maxItems: 1 72 gpio-ranges: 73 minItems: 1 74 maxItems: 16 75 ngpios: 76 description: 77 Number of available gpios in a bank. 78 minimum: 1 79 maximum: 16 80 81 st,bank-name: 82 description: 83 Should be a name string for this bank as specified in the datasheet. 84 $ref: "/schemas/types.yaml#/definitions/string" 85 enum: 86 - GPIOA 87 - GPIOB 88 - GPIOC 89 - GPIOD 90 - GPIOE 91 - GPIOF 92 - GPIOG 93 - GPIOH 94 - GPIOI 95 - GPIOJ 96 - GPIOK 97 - GPIOZ 98 99 st,bank-ioport: 100 description: 101 Should correspond to the EXTI IOport selection (EXTI line used 102 to select GPIOs as interrupts). 103 $ref: "/schemas/types.yaml#/definitions/uint32" 104 minimum: 0 105 maximum: 11 106 107 required: 108 - gpio-controller 109 - '#gpio-cells' 110 - reg 111 - clocks 112 - st,bank-name 113 114 '-[0-9]*$': 115 type: object 116 patternProperties: 117 '^pins': 118 type: object 119 description: | 120 A pinctrl node should contain at least one subnode representing the 121 pinctrl group available on the machine. Each subnode will list the 122 pins it needs, and how they should be configured, with regard to muxer 123 configuration, pullups, drive, output high/low and output speed. 124 properties: 125 pinmux: 126 $ref: "/schemas/types.yaml#/definitions/uint32-array" 127 description: | 128 Integer array, represents gpio pin number and mux setting. 129 Supported pin number and mux varies for different SoCs, and are 130 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 131 These defines are calculated as: ((port * 16 + line) << 8) | function 132 With: 133 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) 134 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) 135 - function: The function number, can be: 136 * 0 : GPIO 137 * 1 : Alternate Function 0 138 * 2 : Alternate Function 1 139 * 3 : Alternate Function 2 140 * ... 141 * 16 : Alternate Function 15 142 * 17 : Analog 143 To simplify the usage, macro is available to generate "pinmux" field. 144 This macro is available here: 145 - include/dt-bindings/pinctrl/stm32-pinfunc.h 146 Some examples of using macro: 147 /* GPIO A9 set as alernate function 2 */ 148 ... { 149 pinmux = <STM32_PINMUX('A', 9, AF2)>; 150 }; 151 /* GPIO A9 set as GPIO */ 152 ... { 153 pinmux = <STM32_PINMUX('A', 9, GPIO)>; 154 }; 155 /* GPIO A9 set as analog */ 156 ... { 157 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; 158 }; 159 160 bias-disable: 161 type: boolean 162 bias-pull-down: 163 type: boolean 164 bias-pull-up: 165 type: boolean 166 drive-push-pull: 167 type: boolean 168 drive-open-drain: 169 type: boolean 170 output-low: 171 type: boolean 172 output-high: 173 type: boolean 174 slew-rate: 175 description: | 176 0: Low speed 177 1: Medium speed 178 2: Fast speed 179 3: High speed 180 $ref: /schemas/types.yaml#/definitions/uint32 181 enum: [0, 1, 2, 3] 182 183 required: 184 - pinmux 185 186required: 187 - compatible 188 - '#address-cells' 189 - '#size-cells' 190 - ranges 191 - pins-are-numbered 192 193additionalProperties: false 194 195examples: 196 - | 197 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 198 #include <dt-bindings/mfd/stm32f4-rcc.h> 199 //Example 1 200 pinctrl@40020000 { 201 #address-cells = <1>; 202 #size-cells = <1>; 203 compatible = "st,stm32f429-pinctrl"; 204 ranges = <0 0x40020000 0x3000>; 205 pins-are-numbered; 206 207 gpioa: gpio@0 { 208 gpio-controller; 209 #gpio-cells = <2>; 210 reg = <0x0 0x400>; 211 resets = <&reset_ahb1 0>; 212 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 213 st,bank-name = "GPIOA"; 214 }; 215 }; 216 217 //Example 2 (using gpio-ranges) 218 pinctrl@50020000 { 219 #address-cells = <1>; 220 #size-cells = <1>; 221 compatible = "st,stm32f429-pinctrl"; 222 ranges = <0 0x50020000 0x3000>; 223 pins-are-numbered; 224 225 gpiob: gpio@1000 { 226 gpio-controller; 227 #gpio-cells = <2>; 228 reg = <0x1000 0x400>; 229 resets = <&reset_ahb1 0>; 230 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 231 st,bank-name = "GPIOB"; 232 gpio-ranges = <&pinctrl 0 0 16>; 233 }; 234 235 gpioc: gpio@2000 { 236 gpio-controller; 237 #gpio-cells = <2>; 238 reg = <0x2000 0x400>; 239 resets = <&reset_ahb1 0>; 240 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 241 st,bank-name = "GPIOC"; 242 ngpios = <5>; 243 gpio-ranges = <&pinctrl 0 16 3>, 244 <&pinctrl 14 30 2>; 245 }; 246 }; 247 248 //Example 3 pin groups 249 pinctrl { 250 usart1_pins_a: usart1-0 { 251 pins1 { 252 pinmux = <STM32_PINMUX('A', 9, AF7)>; 253 bias-disable; 254 drive-push-pull; 255 slew-rate = <0>; 256 }; 257 pins2 { 258 pinmux = <STM32_PINMUX('A', 10, AF7)>; 259 bias-disable; 260 }; 261 }; 262 }; 263 264 usart1 { 265 pinctrl-0 = <&usart1_pins_a>; 266 pinctrl-names = "default"; 267 }; 268 269... 270