1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) STMicroelectronics 2019. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: STM32 GPIO and Pin Mux/Config controller 9 10maintainers: 11 - Alexandre TORGUE <alexandre.torgue@foss.st.com> 12 13description: | 14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware 15 controller. It controls the input/output settings on the available pins and 16 also provides ability to multiplex and configure the output of various 17 on-chip controllers onto these pads. 18 19properties: 20 compatible: 21 enum: 22 - st,stm32f429-pinctrl 23 - st,stm32f469-pinctrl 24 - st,stm32f746-pinctrl 25 - st,stm32f769-pinctrl 26 - st,stm32h743-pinctrl 27 - st,stm32mp135-pinctrl 28 - st,stm32mp157-pinctrl 29 - st,stm32mp157-z-pinctrl 30 31 '#address-cells': 32 const: 1 33 '#size-cells': 34 const: 1 35 36 ranges: true 37 pins-are-numbered: true 38 hwlocks: true 39 40 interrupts: 41 maxItems: 1 42 43 st,syscfg: 44 description: Phandle+args to the syscon node which includes IRQ mux selection. 45 $ref: "/schemas/types.yaml#/definitions/phandle-array" 46 items: 47 - items: 48 - description: syscon node which includes IRQ mux selection 49 - description: The offset of the IRQ mux selection register 50 - description: The field mask of IRQ mux, needed if different of 0xf 51 52 st,package: 53 description: 54 Indicates the SOC package used. 55 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h 56 $ref: /schemas/types.yaml#/definitions/uint32 57 enum: [1, 2, 4, 8] 58 59patternProperties: 60 '^gpio@[0-9a-f]*$': 61 type: object 62 additionalProperties: false 63 properties: 64 gpio-controller: true 65 '#gpio-cells': 66 const: 2 67 interrupt-controller: true 68 '#interrupt-cells': 69 const: 2 70 71 reg: 72 maxItems: 1 73 clocks: 74 maxItems: 1 75 resets: 76 maxItems: 1 77 gpio-line-names: true 78 gpio-ranges: 79 minItems: 1 80 maxItems: 16 81 ngpios: 82 description: 83 Number of available gpios in a bank. 84 minimum: 1 85 maximum: 16 86 87 st,bank-name: 88 description: 89 Should be a name string for this bank as specified in the datasheet. 90 $ref: "/schemas/types.yaml#/definitions/string" 91 enum: 92 - GPIOA 93 - GPIOB 94 - GPIOC 95 - GPIOD 96 - GPIOE 97 - GPIOF 98 - GPIOG 99 - GPIOH 100 - GPIOI 101 - GPIOJ 102 - GPIOK 103 - GPIOZ 104 105 st,bank-ioport: 106 description: 107 Should correspond to the EXTI IOport selection (EXTI line used 108 to select GPIOs as interrupts). 109 $ref: "/schemas/types.yaml#/definitions/uint32" 110 minimum: 0 111 maximum: 11 112 113 patternProperties: 114 "^(.+-hog(-[0-9]+)?)$": 115 type: object 116 required: 117 - gpio-hog 118 119 required: 120 - gpio-controller 121 - '#gpio-cells' 122 - reg 123 - clocks 124 - st,bank-name 125 126 '-[0-9]*$': 127 type: object 128 additionalProperties: false 129 130 patternProperties: 131 '^pins': 132 type: object 133 additionalProperties: false 134 description: | 135 A pinctrl node should contain at least one subnode representing the 136 pinctrl group available on the machine. Each subnode will list the 137 pins it needs, and how they should be configured, with regard to muxer 138 configuration, pullups, drive, output high/low and output speed. 139 properties: 140 pinmux: 141 $ref: "/schemas/types.yaml#/definitions/uint32-array" 142 description: | 143 Integer array, represents gpio pin number and mux setting. 144 Supported pin number and mux varies for different SoCs, and are 145 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 146 These defines are calculated as: ((port * 16 + line) << 8) | function 147 With: 148 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) 149 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) 150 - function: The function number, can be: 151 * 0 : GPIO 152 * 1 : Alternate Function 0 153 * 2 : Alternate Function 1 154 * 3 : Alternate Function 2 155 * ... 156 * 16 : Alternate Function 15 157 * 17 : Analog 158 To simplify the usage, macro is available to generate "pinmux" field. 159 This macro is available here: 160 - include/dt-bindings/pinctrl/stm32-pinfunc.h 161 Some examples of using macro: 162 /* GPIO A9 set as alernate function 2 */ 163 ... { 164 pinmux = <STM32_PINMUX('A', 9, AF2)>; 165 }; 166 /* GPIO A9 set as GPIO */ 167 ... { 168 pinmux = <STM32_PINMUX('A', 9, GPIO)>; 169 }; 170 /* GPIO A9 set as analog */ 171 ... { 172 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; 173 }; 174 175 bias-disable: 176 type: boolean 177 bias-pull-down: 178 type: boolean 179 bias-pull-up: 180 type: boolean 181 drive-push-pull: 182 type: boolean 183 drive-open-drain: 184 type: boolean 185 output-low: 186 type: boolean 187 output-high: 188 type: boolean 189 slew-rate: 190 description: | 191 0: Low speed 192 1: Medium speed 193 2: Fast speed 194 3: High speed 195 $ref: /schemas/types.yaml#/definitions/uint32 196 enum: [0, 1, 2, 3] 197 198 required: 199 - pinmux 200 201allOf: 202 - $ref: "pinctrl.yaml#" 203 204required: 205 - compatible 206 - '#address-cells' 207 - '#size-cells' 208 - ranges 209 - pins-are-numbered 210 211additionalProperties: false 212 213examples: 214 - | 215 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 216 #include <dt-bindings/mfd/stm32f4-rcc.h> 217 //Example 1 218 pinctrl@40020000 { 219 #address-cells = <1>; 220 #size-cells = <1>; 221 compatible = "st,stm32f429-pinctrl"; 222 ranges = <0 0x40020000 0x3000>; 223 pins-are-numbered; 224 225 gpioa: gpio@0 { 226 gpio-controller; 227 #gpio-cells = <2>; 228 reg = <0x0 0x400>; 229 resets = <&reset_ahb1 0>; 230 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 231 st,bank-name = "GPIOA"; 232 }; 233 }; 234 235 //Example 2 (using gpio-ranges) 236 pinctrl@50020000 { 237 #address-cells = <1>; 238 #size-cells = <1>; 239 compatible = "st,stm32f429-pinctrl"; 240 ranges = <0 0x50020000 0x3000>; 241 pins-are-numbered; 242 243 gpiob: gpio@1000 { 244 gpio-controller; 245 #gpio-cells = <2>; 246 reg = <0x1000 0x400>; 247 resets = <&reset_ahb1 0>; 248 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 249 st,bank-name = "GPIOB"; 250 gpio-ranges = <&pinctrl 0 0 16>; 251 }; 252 253 gpioc: gpio@2000 { 254 gpio-controller; 255 #gpio-cells = <2>; 256 reg = <0x2000 0x400>; 257 resets = <&reset_ahb1 0>; 258 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 259 st,bank-name = "GPIOC"; 260 ngpios = <5>; 261 gpio-ranges = <&pinctrl 0 16 3>, 262 <&pinctrl 14 30 2>; 263 }; 264 }; 265 266 //Example 3 pin groups 267 pinctrl { 268 usart1_pins_a: usart1-0 { 269 pins1 { 270 pinmux = <STM32_PINMUX('A', 9, AF7)>; 271 bias-disable; 272 drive-push-pull; 273 slew-rate = <0>; 274 }; 275 pins2 { 276 pinmux = <STM32_PINMUX('A', 10, AF7)>; 277 bias-disable; 278 }; 279 }; 280 }; 281 282 usart1 { 283 pinctrl-0 = <&usart1_pins_a>; 284 pinctrl-names = "default"; 285 }; 286 287... 288