xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12
13description:
14  The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
15  controller.
16  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17  Each port features up to 8 pins, each of them configurable for GPIO function
18  (port mode) or in alternate function mode.
19  Up to 8 different alternate function modes exist for each single pin.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - enum:
26              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
27
28      - items:
29          - enum:
30              - renesas,r9a07g054-pinctrl     # RZ/V2L
31          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
32
33  reg:
34    maxItems: 1
35
36  gpio-controller: true
37
38  '#gpio-cells':
39    const: 2
40    description:
41      The first cell contains the global GPIO port index, constructed using the
42      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
43      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
44      E.g. "RZG2L_GPIO(39, 1)" for P39_1.
45
46  gpio-ranges:
47    maxItems: 1
48
49  clocks:
50    maxItems: 1
51
52  power-domains:
53    maxItems: 1
54
55  resets:
56    items:
57      - description: GPIO_RSTN signal
58      - description: GPIO_PORT_RESETN signal
59      - description: GPIO_SPARE_RESETN signal
60
61additionalProperties:
62  anyOf:
63    - type: object
64      allOf:
65        - $ref: pincfg-node.yaml#
66        - $ref: pinmux-node.yaml#
67
68      description:
69        Pin controller client devices use pin configuration subnodes (children
70        and grandchildren) for desired pin configuration.
71        Client device subnodes use below standard properties.
72
73      properties:
74        phandle: true
75        pinmux:
76          description:
77            Values are constructed from GPIO port number, pin number, and
78            alternate function configuration number using the RZG2L_PORT_PINMUX()
79            helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
80        pins: true
81        drive-strength:
82          enum: [ 2, 4, 8, 12 ]
83        output-impedance-ohms:
84          enum: [ 33, 50, 66, 100 ]
85        power-source:
86          description: I/O voltage in millivolt.
87          enum: [ 1800, 2500, 3300 ]
88        slew-rate: true
89        gpio-hog: true
90        gpios: true
91        input-enable: true
92        output-high: true
93        output-low: true
94        line-name: true
95
96    - type: object
97      properties:
98        phandle: true
99
100      additionalProperties:
101        $ref: "#/additionalProperties/anyOf/0"
102
103allOf:
104  - $ref: "pinctrl.yaml#"
105
106required:
107  - compatible
108  - reg
109  - gpio-controller
110  - '#gpio-cells'
111  - gpio-ranges
112  - clocks
113  - power-domains
114  - resets
115
116examples:
117  - |
118    #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
119    #include <dt-bindings/clock/r9a07g044-cpg.h>
120
121    pinctrl: pinctrl@11030000 {
122            compatible = "renesas,r9a07g044-pinctrl";
123            reg = <0x11030000 0x10000>;
124
125            gpio-controller;
126            #gpio-cells = <2>;
127            gpio-ranges = <&pinctrl 0 0 392>;
128            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
129            resets = <&cpg R9A07G044_GPIO_RSTN>,
130                     <&cpg R9A07G044_GPIO_PORT_RESETN>,
131                     <&cpg R9A07G044_GPIO_SPARE_RESETN>;
132            power-domains = <&cpg>;
133
134            scif0_pins: serial0 {
135                    pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
136                             <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
137            };
138
139            i2c1_pins: i2c1 {
140                    pins = "RIIC1_SDA", "RIIC1_SCL";
141                    input-enable;
142            };
143
144            sd1-pwr-en-hog {
145                    gpio-hog;
146                    gpios = <RZG2L_GPIO(39, 2) 0>;
147                    output-high;
148                    line-name = "sd1_pwr_en";
149            };
150
151            sdhi1_pins: sd1 {
152                    sd1_mux {
153                            pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
154                                     <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
155                            power-source  = <3300>;
156                    };
157
158                    sd1_data {
159                            pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
160                            power-source  = <3300>;
161                    };
162
163                    sd1_ctrl {
164                            pins = "SD1_CLK", "SD1_CMD";
165                            power-source  = <3300>;
166                    };
167            };
168    };
169