1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12 13description: 14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and 15 GPIO controller. 16 Pin multiplexing and GPIO configuration is performed on a per-pin basis. 17 Each port features up to 8 pins, each of them configurable for GPIO function 18 (port mode) or in alternate function mode. 19 Up to 8 different alternate function modes exist for each single pin. 20 21properties: 22 compatible: 23 oneOf: 24 - items: 25 - enum: 26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five 27 - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} 28 29 - items: 30 - enum: 31 - renesas,r9a07g054-pinctrl # RZ/V2L 32 - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L 33 34 reg: 35 maxItems: 1 36 37 gpio-controller: true 38 39 '#gpio-cells': 40 const: 2 41 description: 42 The first cell contains the global GPIO port index, constructed using the 43 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the 44 second cell represents consumer flag as mentioned in ../gpio/gpio.txt 45 E.g. "RZG2L_GPIO(39, 1)" for P39_1. 46 47 gpio-ranges: 48 maxItems: 1 49 50 interrupt-controller: true 51 52 '#interrupt-cells': 53 const: 2 54 description: 55 The first cell contains the global GPIO port index, constructed using the 56 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the 57 second cell is used to specify the flag. 58 E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is 59 being used as an interrupt. 60 61 clocks: 62 maxItems: 1 63 64 power-domains: 65 maxItems: 1 66 67 resets: 68 items: 69 - description: GPIO_RSTN signal 70 - description: GPIO_PORT_RESETN signal 71 - description: GPIO_SPARE_RESETN signal 72 73additionalProperties: 74 anyOf: 75 - type: object 76 allOf: 77 - $ref: pincfg-node.yaml# 78 - $ref: pinmux-node.yaml# 79 80 description: 81 Pin controller client devices use pin configuration subnodes (children 82 and grandchildren) for desired pin configuration. 83 Client device subnodes use below standard properties. 84 85 properties: 86 pinmux: 87 description: 88 Values are constructed from GPIO port number, pin number, and 89 alternate function configuration number using the RZG2L_PORT_PINMUX() 90 helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>. 91 pins: true 92 drive-strength: 93 enum: [ 2, 4, 8, 12 ] 94 output-impedance-ohms: 95 enum: [ 33, 50, 66, 100 ] 96 power-source: 97 description: I/O voltage in millivolt. 98 enum: [ 1800, 2500, 3300 ] 99 slew-rate: true 100 gpio-hog: true 101 gpios: true 102 input-enable: true 103 output-high: true 104 output-low: true 105 line-name: true 106 107 - type: object 108 additionalProperties: 109 $ref: "#/additionalProperties/anyOf/0" 110 111allOf: 112 - $ref: pinctrl.yaml# 113 114required: 115 - compatible 116 - reg 117 - gpio-controller 118 - '#gpio-cells' 119 - gpio-ranges 120 - interrupt-controller 121 - '#interrupt-cells' 122 - clocks 123 - power-domains 124 - resets 125 126examples: 127 - | 128 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 129 #include <dt-bindings/clock/r9a07g044-cpg.h> 130 131 pinctrl: pinctrl@11030000 { 132 compatible = "renesas,r9a07g044-pinctrl"; 133 reg = <0x11030000 0x10000>; 134 135 gpio-controller; 136 #gpio-cells = <2>; 137 gpio-ranges = <&pinctrl 0 0 392>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 141 resets = <&cpg R9A07G044_GPIO_RSTN>, 142 <&cpg R9A07G044_GPIO_PORT_RESETN>, 143 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 144 power-domains = <&cpg>; 145 146 scif0_pins: serial0 { 147 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */ 148 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */ 149 }; 150 151 i2c1_pins: i2c1 { 152 pins = "RIIC1_SDA", "RIIC1_SCL"; 153 input-enable; 154 }; 155 156 sd1-pwr-en-hog { 157 gpio-hog; 158 gpios = <RZG2L_GPIO(39, 2) 0>; 159 output-high; 160 line-name = "sd1_pwr_en"; 161 }; 162 163 sdhi1_pins: sd1 { 164 sd1_mux { 165 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */ 166 <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */ 167 power-source = <3300>; 168 }; 169 170 sd1_data { 171 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; 172 power-source = <3300>; 173 }; 174 175 sd1_ctrl { 176 pins = "SD1_CLK", "SD1_CMD"; 177 power-source = <3300>; 178 }; 179 }; 180 }; 181