1Qualcomm Atheros IPQ4019 TLMM block 2 3This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019 4platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities. 5 6Required properties: 7- compatible: "qcom,ipq4019-pinctrl" 8- reg: Should be the base address and length of the TLMM block. 9- interrupts: Should be the parent IRQ of the TLMM block. 10- interrupt-controller: Marks the device node as an interrupt controller. 11- #interrupt-cells: Should be two. 12- gpio-controller: Marks the device node as a GPIO controller. 13- #gpio-cells : Should be two. 14 The first cell is the gpio pin number and the 15 second cell is used for optional parameters. 16- gpio-ranges: see ../gpio/gpio.txt 17 18Optional properties: 19 20- gpio-reserved-ranges: see ../gpio/gpio.txt 21 22Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 23a general description of GPIO and interrupt bindings. 24 25Please refer to pinctrl-bindings.txt in this directory for details of the 26common pinctrl bindings used by client devices, including the meaning of the 27phrase "pin configuration node". 28 29The pin configuration nodes act as a container for an arbitrary number of 30subnodes. Each of these subnodes represents some desired configuration for a 31pin, a group, or a list of pins or groups. This configuration can include the 32mux function to select on those pin(s)/group(s), and various pin configuration 33parameters, such as pull-up, drive strength, etc. 34 35The name of each subnode is not important; all subnodes should be enumerated 36and processed purely based on their content. 37 38Each subnode only affects those parameters that are explicitly listed. In 39other words, a subnode that lists a mux function but no pin configuration 40parameters implies no information about any pin configuration parameters. 41Similarly, a pin subnode that describes a pullup parameter implies no 42information about e.g. the mux function. 43 44 45The following generic properties as defined in pinctrl-bindings.txt are valid 46to specify in a pin configuration subnode: 47 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, 48 drive-strength. 49 50Non-empty subnodes must specify the 'pins' property. 51Note that not all properties are valid for all pins. 52 53 54Valid values for qcom,pins are: 55 gpio0-gpio99 56 Supports mux, bias and drive-strength 57 58Valid values for qcom,function are: 59aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0, 60blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx, 61jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11, 62mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1, 63smart2, smart3, tm, wifi0, wifi1 64 65Example: 66 67 tlmm: pinctrl@1000000 { 68 compatible = "qcom,ipq4019-pinctrl"; 69 reg = <0x1000000 0x300000>; 70 71 gpio-controller; 72 #gpio-cells = <2>; 73 gpio-ranges = <&tlmm 0 0 100>; 74 interrupt-controller; 75 #interrupt-cells = <2>; 76 interrupts = <0 208 0>; 77 78 serial_pins: serial_pinmux { 79 mux { 80 pins = "gpio60", "gpio61"; 81 function = "blsp_uart0"; 82 bias-disable; 83 }; 84 }; 85 }; 86