1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0-only 2*c66ec88fSEmmanuel Vadot%YAML 1.2 3*c66ec88fSEmmanuel Vadot--- 4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml# 5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadottitle: Generic pin multiplexing node schema 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadotmaintainers: 10*c66ec88fSEmmanuel Vadot - Linus Walleij <linus.walleij@linaro.org> 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadotdescription: | 13*c66ec88fSEmmanuel Vadot The contents of the pin configuration child nodes are defined by the binding 14*c66ec88fSEmmanuel Vadot for the individual pin controller device. The pin configuration nodes need not 15*c66ec88fSEmmanuel Vadot be direct children of the pin controller device; they may be grandchildren, 16*c66ec88fSEmmanuel Vadot for example. Whether this is legal, and whether there is any interaction 17*c66ec88fSEmmanuel Vadot between the child and intermediate parent nodes, is again defined entirely by 18*c66ec88fSEmmanuel Vadot the binding for the individual pin controller device. 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel Vadot While not required to be used, there are 3 generic forms of pin muxing nodes 21*c66ec88fSEmmanuel Vadot which pin controller devices can use. 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot pin multiplexing nodes: 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel Vadot Example: 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel Vadot state_0_node_a { 28*c66ec88fSEmmanuel Vadot uart0 { 29*c66ec88fSEmmanuel Vadot function = "uart0"; 30*c66ec88fSEmmanuel Vadot groups = "u0rxtx", "u0rtscts"; 31*c66ec88fSEmmanuel Vadot }; 32*c66ec88fSEmmanuel Vadot }; 33*c66ec88fSEmmanuel Vadot state_1_node_a { 34*c66ec88fSEmmanuel Vadot spi0 { 35*c66ec88fSEmmanuel Vadot function = "spi0"; 36*c66ec88fSEmmanuel Vadot groups = "spi0pins"; 37*c66ec88fSEmmanuel Vadot }; 38*c66ec88fSEmmanuel Vadot }; 39*c66ec88fSEmmanuel Vadot state_2_node_a { 40*c66ec88fSEmmanuel Vadot function = "i2c0"; 41*c66ec88fSEmmanuel Vadot pins = "mfio29", "mfio30"; 42*c66ec88fSEmmanuel Vadot }; 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel Vadot Optionally an alternative binding can be used if more suitable depending on the 45*c66ec88fSEmmanuel Vadot pin controller hardware. For hardware where there is a large number of identical 46*c66ec88fSEmmanuel Vadot pin controller instances, naming each pin and function can easily become 47*c66ec88fSEmmanuel Vadot unmaintainable. This is especially the case if the same controller is used for 48*c66ec88fSEmmanuel Vadot different pins and functions depending on the SoC revision and packaging. 49*c66ec88fSEmmanuel Vadot 50*c66ec88fSEmmanuel Vadot For cases like this, the pin controller driver may use pinctrl-pin-array helper 51*c66ec88fSEmmanuel Vadot binding with a hardware based index and a number of pin configuration values: 52*c66ec88fSEmmanuel Vadot 53*c66ec88fSEmmanuel Vadot pincontroller { 54*c66ec88fSEmmanuel Vadot ... /* Standard DT properties for the device itself elided */ 55*c66ec88fSEmmanuel Vadot #pinctrl-cells = <2>; 56*c66ec88fSEmmanuel Vadot 57*c66ec88fSEmmanuel Vadot state_0_node_a { 58*c66ec88fSEmmanuel Vadot pinctrl-pin-array = < 59*c66ec88fSEmmanuel Vadot 0 A_DELAY_PS(0) G_DELAY_PS(120) 60*c66ec88fSEmmanuel Vadot 4 A_DELAY_PS(0) G_DELAY_PS(360) 61*c66ec88fSEmmanuel Vadot ... 62*c66ec88fSEmmanuel Vadot >; 63*c66ec88fSEmmanuel Vadot }; 64*c66ec88fSEmmanuel Vadot ... 65*c66ec88fSEmmanuel Vadot }; 66*c66ec88fSEmmanuel Vadot 67*c66ec88fSEmmanuel Vadot Above #pinctrl-cells specifies the number of value cells in addition to the 68*c66ec88fSEmmanuel Vadot index of the registers. This is similar to the interrupts-extended binding with 69*c66ec88fSEmmanuel Vadot one exception. There is no need to specify the phandle for each entry as that 70*c66ec88fSEmmanuel Vadot is already known as the defined pins are always children of the pin controller 71*c66ec88fSEmmanuel Vadot node. Further having the phandle pointing to another pin controller would not 72*c66ec88fSEmmanuel Vadot currently work as the pinctrl framework uses named modes to group pins for each 73*c66ec88fSEmmanuel Vadot pin control device. 74*c66ec88fSEmmanuel Vadot 75*c66ec88fSEmmanuel Vadot The index for pinctrl-pin-array must relate to the hardware for the pinctrl 76*c66ec88fSEmmanuel Vadot registers, and must not be a virtual index of pin instances. The reason for 77*c66ec88fSEmmanuel Vadot this is to avoid mapping of the index in the dts files and the pin controller 78*c66ec88fSEmmanuel Vadot driver as it can change. 79*c66ec88fSEmmanuel Vadot 80*c66ec88fSEmmanuel Vadot For hardware where pin multiplexing configurations have to be specified for 81*c66ec88fSEmmanuel Vadot each single pin the number of required sub-nodes containing "pin" and 82*c66ec88fSEmmanuel Vadot "function" properties can quickly escalate and become hard to write and 83*c66ec88fSEmmanuel Vadot maintain. 84*c66ec88fSEmmanuel Vadot 85*c66ec88fSEmmanuel Vadot For cases like this, the pin controller driver may use the pinmux helper 86*c66ec88fSEmmanuel Vadot property, where the pin identifier is provided with mux configuration settings 87*c66ec88fSEmmanuel Vadot in a pinmux group. A pinmux group consists of the pin identifier and mux 88*c66ec88fSEmmanuel Vadot settings represented as a single integer or an array of integers. 89*c66ec88fSEmmanuel Vadot 90*c66ec88fSEmmanuel Vadot The pinmux property accepts an array of pinmux groups, each of them describing 91*c66ec88fSEmmanuel Vadot a single pin multiplexing configuration. 92*c66ec88fSEmmanuel Vadot 93*c66ec88fSEmmanuel Vadot pincontroller { 94*c66ec88fSEmmanuel Vadot state_0_node_a { 95*c66ec88fSEmmanuel Vadot pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...; 96*c66ec88fSEmmanuel Vadot }; 97*c66ec88fSEmmanuel Vadot }; 98*c66ec88fSEmmanuel Vadot 99*c66ec88fSEmmanuel Vadot Each individual pin controller driver bindings documentation shall specify 100*c66ec88fSEmmanuel Vadot how pin IDs and pin multiplexing configuration are defined and assembled 101*c66ec88fSEmmanuel Vadot together in a pinmux group. 102*c66ec88fSEmmanuel Vadot 103*c66ec88fSEmmanuel Vadotproperties: 104*c66ec88fSEmmanuel Vadot function: 105*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/string 106*c66ec88fSEmmanuel Vadot description: The mux function to select 107*c66ec88fSEmmanuel Vadot 108*c66ec88fSEmmanuel Vadot pins: 109*c66ec88fSEmmanuel Vadot oneOf: 110*c66ec88fSEmmanuel Vadot - $ref: /schemas/types.yaml#/definitions/uint32-array 111*c66ec88fSEmmanuel Vadot - $ref: /schemas/types.yaml#/definitions/string-array 112*c66ec88fSEmmanuel Vadot description: 113*c66ec88fSEmmanuel Vadot The list of pin identifiers that properties in the node apply to. The 114*c66ec88fSEmmanuel Vadot specific binding for the hardware defines whether the entries are integers 115*c66ec88fSEmmanuel Vadot or strings, and their meaning. 116*c66ec88fSEmmanuel Vadot 117*c66ec88fSEmmanuel Vadot groups: 118*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/string-array 119*c66ec88fSEmmanuel Vadot description: 120*c66ec88fSEmmanuel Vadot the group to apply the properties to, if the driver supports 121*c66ec88fSEmmanuel Vadot configuration of whole groups rather than individual pins (either 122*c66ec88fSEmmanuel Vadot this, "pins" or "pinmux" has to be specified) 123*c66ec88fSEmmanuel Vadot 124*c66ec88fSEmmanuel Vadot pinmux: 125*c66ec88fSEmmanuel Vadot description: 126*c66ec88fSEmmanuel Vadot The list of numeric pin ids and their mux settings that properties in the 127*c66ec88fSEmmanuel Vadot node apply to (either this, "pins" or "groups" have to be specified) 128*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32-array 129*c66ec88fSEmmanuel Vadot 130*c66ec88fSEmmanuel Vadot pinctrl-pin-array: 131*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32-array 132