xref: /freebsd/sys/contrib/device-tree/Bindings/phy/samsung,usb3-drd-phy.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Marek Szyprowski <m.szyprowski@samsung.com>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13
14description: |
15  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16  compatible PHYs, the second cell in the PHY specifier identifies the
17  PHY id, which is interpreted as follows::
18    0 - UTMI+ type phy,
19    1 - PIPE3 type phy.
20
21  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
24
25properties:
26  compatible:
27    enum:
28      - google,gs101-usb31drd-phy
29      - samsung,exynos2200-usb32drd-phy
30      - samsung,exynos5250-usbdrd-phy
31      - samsung,exynos5420-usbdrd-phy
32      - samsung,exynos5433-usbdrd-phy
33      - samsung,exynos7-usbdrd-phy
34      - samsung,exynos7870-usbdrd-phy
35      - samsung,exynos850-usbdrd-phy
36      - samsung,exynos990-usbdrd-phy
37
38  clocks:
39    minItems: 1
40    maxItems: 5
41
42  clock-names:
43    minItems: 1
44    maxItems: 5
45    description: |
46      Typically two clocks:
47        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
48          for register access.
49        - PHY reference clock (usually crystal clock), used for PHY operations,
50          associated by phy name. It is used to determine bit values for clock
51          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
52          in the CMU. It's not needed for Exynos2200.
53
54  "#phy-cells":
55    const: 1
56
57  phys:
58    maxItems: 1
59    description:
60      USBDRD-underlying high-speed PHY
61
62  phy-names:
63    const: hs
64
65  port:
66    $ref: /schemas/graph.yaml#/properties/port
67    description:
68      Any connector to the data bus of this controller should be modelled using
69      the OF graph bindings specified.
70
71  reg:
72    minItems: 1
73    maxItems: 3
74
75  reg-names:
76    minItems: 1
77    items:
78      - const: phy
79      - const: pcs
80      - const: pma
81
82  samsung,pmu-syscon:
83    $ref: /schemas/types.yaml#/definitions/phandle
84    description:
85      Phandle to PMU system controller interface.
86
87  vbus-supply:
88    description:
89      VBUS power source.
90
91  vbus-boost-supply:
92    description:
93      VBUS Boost 5V power source.
94
95  pll-supply:
96    description: Power supply for the USB PLL.
97
98  dvdd-usb20-supply:
99    description: DVDD power supply for the USB 2.0 phy.
100
101  vddh-usb20-supply:
102    description: VDDh power supply for the USB 2.0 phy.
103
104  vdd33-usb20-supply:
105    description: 3.3V power supply for the USB 2.0 phy.
106
107  vdda-usbdp-supply:
108    description: VDDa power supply for the USB DP phy.
109
110  vddh-usbdp-supply:
111    description: VDDh power supply for the USB DP phy.
112
113required:
114  - compatible
115  - clocks
116  - clock-names
117  - "#phy-cells"
118  - reg
119  - samsung,pmu-syscon
120
121allOf:
122  - if:
123      properties:
124        compatible:
125          contains:
126            const: google,gs101-usb31drd-phy
127    then:
128      $ref: /schemas/usb/usb-switch.yaml#
129
130      properties:
131        clocks:
132          items:
133            - description: Gate of main PHY clock
134            - description: Gate of PHY reference clock
135            - description: Gate of control interface AXI clock
136            - description: Gate of control interface APB clock
137            - description: Gate of SCL APB clock
138
139        clock-names:
140          items:
141            - const: phy
142            - const: ref
143            - const: ctrl_aclk
144            - const: ctrl_pclk
145            - const: scl_pclk
146
147        reg:
148          minItems: 3
149
150        reg-names:
151          minItems: 3
152
153      required:
154        - reg-names
155        - orientation-switch
156        - port
157        - pll-supply
158        - dvdd-usb20-supply
159        - vddh-usb20-supply
160        - vdd33-usb20-supply
161        - vdda-usbdp-supply
162        - vddh-usbdp-supply
163
164  - if:
165      properties:
166        compatible:
167          contains:
168            enum:
169              - samsung,exynos2200-usb32drd-phy
170    then:
171      properties:
172        clocks:
173          maxItems: 1
174        clock-names:
175          items:
176            - const: phy
177        reg:
178          maxItems: 1
179        reg-names:
180          maxItems: 1
181      required:
182        - phys
183        - phy-names
184
185  - if:
186      properties:
187        compatible:
188          contains:
189            enum:
190              - samsung,exynos5433-usbdrd-phy
191              - samsung,exynos7-usbdrd-phy
192    then:
193      properties:
194        clocks:
195          minItems: 5
196          maxItems: 5
197
198        clock-names:
199          items:
200            - const: phy
201            - const: ref
202            - const: phy_utmi
203            - const: phy_pipe
204            - const: itp
205
206        reg:
207          maxItems: 1
208
209        reg-names:
210          maxItems: 1
211
212  - if:
213      properties:
214        compatible:
215          contains:
216            enum:
217              - samsung,exynos5250-usbdrd-phy
218              - samsung,exynos5420-usbdrd-phy
219              - samsung,exynos7870-usbdrd-phy
220              - samsung,exynos850-usbdrd-phy
221              - samsung,exynos990-usbdrd-phy
222    then:
223      properties:
224        clocks:
225          minItems: 2
226          maxItems: 2
227
228        clock-names:
229          items:
230            - const: phy
231            - const: ref
232
233        reg:
234          maxItems: 1
235
236        reg-names:
237          maxItems: 1
238
239unevaluatedProperties: false
240
241examples:
242  - |
243    #include <dt-bindings/clock/exynos5420.h>
244
245    phy@12100000 {
246        compatible = "samsung,exynos5420-usbdrd-phy";
247        reg = <0x12100000 0x100>;
248        #phy-cells = <1>;
249        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
250        clock-names = "phy", "ref";
251        samsung,pmu-syscon = <&pmu_system_controller>;
252        vbus-supply = <&usb300_vbus_reg>;
253    };
254