1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER 8 9maintainers: 10 - Ansuel Smith <ansuelsmth@gmail.com> 11 12description: 13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer 14 controllers used in ipq806x. Each DWC3 PHY controller should have its 15 own node. 16 17properties: 18 compatible: 19 const: qcom,ipq806x-usb-phy-ss 20 21 "#phy-cells": 22 const: 0 23 24 reg: 25 maxItems: 1 26 27 clocks: 28 minItems: 1 29 maxItems: 2 30 31 clock-names: 32 minItems: 1 33 items: 34 - const: ref 35 - const: xo 36 37 qcom,rx-eq: 38 $ref: /schemas/types.yaml#/definitions/uint32 39 description: Override value for rx_eq. 40 default: 4 41 maximum: 7 42 43 qcom,tx-deamp-3_5db: 44 $ref: /schemas/types.yaml#/definitions/uint32 45 description: Override value for transmit preemphasis. 46 default: 23 47 maximum: 63 48 49 qcom,mpll: 50 $ref: /schemas/types.yaml#/definitions/uint32 51 description: Override value for mpll. 52 default: 0 53 maximum: 7 54 55required: 56 - compatible 57 - "#phy-cells" 58 - reg 59 - clocks 60 - clock-names 61 62additionalProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 67 68 ss_phy_0: phy@110f8830 { 69 compatible = "qcom,ipq806x-usb-phy-ss"; 70 reg = <0x110f8830 0x30>; 71 clocks = <&gcc USB30_0_MASTER_CLK>; 72 clock-names = "ref"; 73 #phy-cells = <0>; 74 }; 75