1MediaTek T-PHY binding 2-------------------------- 3 4T-phy controller supports physical layer functionality for a number of 5controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. 6 7Required properties (controller (parent) node): 8 - compatible : should be one of 9 "mediatek,generic-tphy-v1" 10 "mediatek,generic-tphy-v2" 11 "mediatek,mt2701-u3phy" (deprecated) 12 "mediatek,mt2712-u3phy" (deprecated) 13 "mediatek,mt8173-u3phy"; 14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and 15 "mediatek,generic-tphy-v2" on mt2712 instead. 16 17- #address-cells: the number of cells used to represent physical 18 base addresses. 19- #size-cells: the number of cells used to represent the size of an address. 20- ranges: the address mapping relationship to the parent, defined with 21 - empty value: if optional 'reg' is used. 22 - non-empty value: if optional 'reg' is not used. should set 23 the child's base address to 0, the physical address 24 within parent's address space, and the length of 25 the address map. 26 27Required nodes : a sub-node is required for each port the controller 28 provides. Address range information including the usual 29 'reg' property is used inside these nodes to describe 30 the controller's topology. 31 32Optional properties (controller (parent) node): 33 - reg : offset and length of register shared by multiple ports, 34 exclude port's private register. It is needed on mt2701 35 and mt8173, but not on mt2712. 36 - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate 37 calibrate 38 - mediatek,src-coef : coefficient for slew rate calibrate, depends on 39 SoC process 40 41Required properties (port (child) node): 42- reg : address and length of the register set for the port. 43- #phy-cells : should be 1 (See second example) 44 cell after port phandle is phy type from: 45 - PHY_TYPE_USB2 46 - PHY_TYPE_USB3 47 - PHY_TYPE_PCIE 48 - PHY_TYPE_SATA 49 50Optional properties (PHY_TYPE_USB2 port (child) node): 51- clocks : a list of phandle + clock-specifier pairs, one for each 52 entry in clock-names 53- clock-names : may contain 54 "ref": 48M reference clock for HighSpeed (digital) phy; and 26M 55 reference clock for SuperSpeed (digital) phy, sometimes is 56 24M, 25M or 27M, depended on platform. 57 "da_ref": the reference clock of analog phy, used if the clocks 58 of analog and digital phys are separated, otherwise uses 59 "ref" clock only if needed. 60 61- mediatek,eye-src : u32, the value of slew rate calibrate 62- mediatek,eye-vrt : u32, the selection of VRT reference voltage 63- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage 64- mediatek,bc12 : bool, enable BC12 of u2phy if support it 65- mediatek,discth : u32, the selection of disconnect threshold 66- mediatek,intr : u32, the selection of internal R (resistance) 67 68Example: 69 70u3phy: usb-phy@11290000 { 71 compatible = "mediatek,mt8173-u3phy"; 72 reg = <0 0x11290000 0 0x800>; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 u2port0: usb-phy@11290800 { 78 reg = <0 0x11290800 0 0x100>; 79 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 80 clock-names = "ref"; 81 #phy-cells = <1>; 82 }; 83 84 u3port0: usb-phy@11290900 { 85 reg = <0 0x11290800 0 0x700>; 86 clocks = <&clk26m>; 87 clock-names = "ref"; 88 #phy-cells = <1>; 89 }; 90 91 u2port1: usb-phy@11291000 { 92 reg = <0 0x11291000 0 0x100>; 93 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 94 clock-names = "ref"; 95 #phy-cells = <1>; 96 }; 97}; 98 99Specifying phy control of devices 100--------------------------------- 101 102Device nodes should specify the configuration required in their "phys" 103property, containing a phandle to the phy port node and a device type; 104phy-names for each port are optional. 105 106Example: 107 108#include <dt-bindings/phy/phy.h> 109 110usb30: usb@11270000 { 111 ... 112 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 113 phy-names = "usb2-0", "usb3-0"; 114 ... 115}; 116 117 118Layout differences of banks between mt8173/mt2701 and mt2712 119------------------------------------------------------------- 120mt8173 and mt2701: 121port offset bank 122shared 0x0000 SPLLC 123 0x0100 FMREG 124u2 port0 0x0800 U2PHY_COM 125u3 port0 0x0900 U3PHYD 126 0x0a00 U3PHYD_BANK2 127 0x0b00 U3PHYA 128 0x0c00 U3PHYA_DA 129u2 port1 0x1000 U2PHY_COM 130u3 port1 0x1100 U3PHYD 131 0x1200 U3PHYD_BANK2 132 0x1300 U3PHYA 133 0x1400 U3PHYA_DA 134u2 port2 0x1800 U2PHY_COM 135 ... 136 137mt2712: 138port offset bank 139u2 port0 0x0000 MISC 140 0x0100 FMREG 141 0x0300 U2PHY_COM 142u3 port0 0x0700 SPLLC 143 0x0800 CHIP 144 0x0900 U3PHYD 145 0x0a00 U3PHYD_BANK2 146 0x0b00 U3PHYA 147 0x0c00 U3PHYA_DA 148u2 port1 0x1000 MISC 149 0x1100 FMREG 150 0x1300 U2PHY_COM 151u3 port1 0x1700 SPLLC 152 0x1800 CHIP 153 0x1900 U3PHYD 154 0x1a00 U3PHYD_BANK2 155 0x1b00 U3PHYA 156 0x1c00 U3PHYA_DA 157u2 port2 0x2000 MISC 158 ... 159 160 SPLLC shared by u3 ports and FMREG shared by u2 ports on 161mt8173/mt2701 are put back into each port; a new bank MISC for 162u2 ports and CHIP for u3 ports are added on mt2712. 163