1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller Device Tree Bindings 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2. 63 64properties: 65 $nodename: 66 pattern: "^t-phy@[0-9a-f]+$" 67 68 compatible: 69 oneOf: 70 - items: 71 - enum: 72 - mediatek,mt2701-tphy 73 - mediatek,mt7623-tphy 74 - mediatek,mt7622-tphy 75 - mediatek,mt8516-tphy 76 - const: mediatek,generic-tphy-v1 77 - items: 78 - enum: 79 - mediatek,mt2712-tphy 80 - mediatek,mt7629-tphy 81 - mediatek,mt8183-tphy 82 - mediatek,mt8195-tphy 83 - const: mediatek,generic-tphy-v2 84 - const: mediatek,mt2701-u3phy 85 deprecated: true 86 - const: mediatek,mt2712-u3phy 87 deprecated: true 88 - const: mediatek,mt8173-u3phy 89 90 reg: 91 description: 92 Register shared by multiple ports, exclude port's private register. 93 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 94 T-PHY V2, such as mt2712. 95 maxItems: 1 96 97 "#address-cells": 98 enum: [1, 2] 99 100 "#size-cells": 101 enum: [1, 2] 102 103 # Used with non-empty value if optional 'reg' is not provided. 104 # The format of the value is an arbitrary number of triplets of 105 # (child-bus-address, parent-bus-address, length). 106 ranges: true 107 108 mediatek,src-ref-clk-mhz: 109 description: 110 Frequency of reference clock for slew rate calibrate 111 default: 26 112 113 mediatek,src-coef: 114 description: 115 Coefficient for slew rate calibrate, depends on SoC process 116 $ref: /schemas/types.yaml#/definitions/uint32 117 default: 28 118 119# Required child node: 120patternProperties: 121 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 122 type: object 123 description: 124 A sub-node is required for each port the controller provides. 125 Address range information including the usual 'reg' property 126 is used inside these nodes to describe the controller's topology. 127 128 properties: 129 reg: 130 maxItems: 1 131 132 clocks: 133 minItems: 1 134 maxItems: 2 135 items: 136 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 137 - description: Reference clock of analog phy 138 description: 139 Uses both clocks if the clock of analog and digital phys are 140 separated, otherwise uses "ref" clock only if needed. 141 142 clock-names: 143 minItems: 1 144 maxItems: 2 145 items: 146 - const: ref 147 - const: da_ref 148 149 "#phy-cells": 150 const: 1 151 description: | 152 The cells contain the following arguments. 153 154 - description: The PHY type 155 enum: 156 - PHY_TYPE_USB2 157 - PHY_TYPE_USB3 158 - PHY_TYPE_PCIE 159 - PHY_TYPE_SATA 160 161 # The following optional vendor properties are only for debug or HQA test 162 mediatek,eye-src: 163 description: 164 The value of slew rate calibrate (U2 phy) 165 $ref: /schemas/types.yaml#/definitions/uint32 166 minimum: 1 167 maximum: 7 168 169 mediatek,eye-vrt: 170 description: 171 The selection of VRT reference voltage (U2 phy) 172 $ref: /schemas/types.yaml#/definitions/uint32 173 minimum: 1 174 maximum: 7 175 176 mediatek,eye-term: 177 description: 178 The selection of HS_TX TERM reference voltage (U2 phy) 179 $ref: /schemas/types.yaml#/definitions/uint32 180 minimum: 1 181 maximum: 7 182 183 mediatek,intr: 184 description: 185 The selection of internal resistor (U2 phy) 186 $ref: /schemas/types.yaml#/definitions/uint32 187 minimum: 1 188 maximum: 31 189 190 mediatek,discth: 191 description: 192 The selection of disconnect threshold (U2 phy) 193 $ref: /schemas/types.yaml#/definitions/uint32 194 minimum: 1 195 maximum: 15 196 197 mediatek,bc12: 198 description: 199 Specify the flag to enable BC1.2 if support it 200 type: boolean 201 202 required: 203 - reg 204 - "#phy-cells" 205 206 additionalProperties: false 207 208required: 209 - compatible 210 - "#address-cells" 211 - "#size-cells" 212 - ranges 213 214additionalProperties: false 215 216examples: 217 - | 218 #include <dt-bindings/clock/mt8173-clk.h> 219 #include <dt-bindings/interrupt-controller/arm-gic.h> 220 #include <dt-bindings/interrupt-controller/irq.h> 221 #include <dt-bindings/phy/phy.h> 222 usb@11271000 { 223 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 224 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 225 reg-names = "mac", "ippc"; 226 phys = <&u2port0 PHY_TYPE_USB2>, 227 <&u3port0 PHY_TYPE_USB3>, 228 <&u2port1 PHY_TYPE_USB2>; 229 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 230 clocks = <&topckgen CLK_TOP_USB30_SEL>; 231 clock-names = "sys_ck"; 232 }; 233 234 t-phy@11290000 { 235 compatible = "mediatek,mt8173-u3phy"; 236 reg = <0x11290000 0x800>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 ranges; 240 241 u2port0: usb-phy@11290800 { 242 reg = <0x11290800 0x100>; 243 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 244 clock-names = "ref", "da_ref"; 245 #phy-cells = <1>; 246 }; 247 248 u3port0: usb-phy@11290900 { 249 reg = <0x11290900 0x700>; 250 clocks = <&clk26m>; 251 clock-names = "ref"; 252 #phy-cells = <1>; 253 }; 254 255 u2port1: usb-phy@11291000 { 256 reg = <0x11291000 0x100>; 257 #phy-cells = <1>; 258 }; 259 }; 260 261... 262