1*354d7675SEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*354d7675SEmmanuel Vadot%YAML 1.2 3*354d7675SEmmanuel Vadot--- 4*354d7675SEmmanuel Vadot$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# 5*354d7675SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*354d7675SEmmanuel Vadot 7*354d7675SEmmanuel Vadottitle: HiSilicon Kirin970 PCIe PHY 8*354d7675SEmmanuel Vadot 9*354d7675SEmmanuel Vadotmaintainers: 10*354d7675SEmmanuel Vadot - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 11*354d7675SEmmanuel Vadot 12*354d7675SEmmanuel Vadotdescription: |+ 13*354d7675SEmmanuel Vadot Bindings for PCIe PHY on HiSilicon Kirin 970. 14*354d7675SEmmanuel Vadot 15*354d7675SEmmanuel Vadotproperties: 16*354d7675SEmmanuel Vadot compatible: 17*354d7675SEmmanuel Vadot const: hisilicon,hi970-pcie-phy 18*354d7675SEmmanuel Vadot 19*354d7675SEmmanuel Vadot "#phy-cells": 20*354d7675SEmmanuel Vadot const: 0 21*354d7675SEmmanuel Vadot 22*354d7675SEmmanuel Vadot reg: 23*354d7675SEmmanuel Vadot maxItems: 1 24*354d7675SEmmanuel Vadot description: PHY Control registers 25*354d7675SEmmanuel Vadot 26*354d7675SEmmanuel Vadot phy-supply: 27*354d7675SEmmanuel Vadot description: The PCIe PHY power supply 28*354d7675SEmmanuel Vadot 29*354d7675SEmmanuel Vadot clocks: 30*354d7675SEmmanuel Vadot items: 31*354d7675SEmmanuel Vadot - description: PCIe PHY clock 32*354d7675SEmmanuel Vadot - description: PCIe AUX clock 33*354d7675SEmmanuel Vadot - description: PCIe APB PHY clock 34*354d7675SEmmanuel Vadot - description: PCIe APB SYS clock 35*354d7675SEmmanuel Vadot - description: PCIe ACLK clock 36*354d7675SEmmanuel Vadot 37*354d7675SEmmanuel Vadot clock-names: 38*354d7675SEmmanuel Vadot items: 39*354d7675SEmmanuel Vadot - const: phy_ref 40*354d7675SEmmanuel Vadot - const: aux 41*354d7675SEmmanuel Vadot - const: apb_phy 42*354d7675SEmmanuel Vadot - const: apb_sys 43*354d7675SEmmanuel Vadot - const: aclk 44*354d7675SEmmanuel Vadot 45*354d7675SEmmanuel Vadot hisilicon,eye-diagram-param: 46*354d7675SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32-array 47*354d7675SEmmanuel Vadot description: Eye diagram for phy. 48*354d7675SEmmanuel Vadot 49*354d7675SEmmanuel Vadotrequired: 50*354d7675SEmmanuel Vadot - "#phy-cells" 51*354d7675SEmmanuel Vadot - compatible 52*354d7675SEmmanuel Vadot - reg 53*354d7675SEmmanuel Vadot - clocks 54*354d7675SEmmanuel Vadot - clock-names 55*354d7675SEmmanuel Vadot - hisilicon,eye-diagram-param 56*354d7675SEmmanuel Vadot - phy-supply 57*354d7675SEmmanuel Vadot 58*354d7675SEmmanuel VadotadditionalProperties: false 59*354d7675SEmmanuel Vadot 60*354d7675SEmmanuel Vadotexamples: 61*354d7675SEmmanuel Vadot - | 62*354d7675SEmmanuel Vadot #include <dt-bindings/clock/hi3670-clock.h> 63*354d7675SEmmanuel Vadot 64*354d7675SEmmanuel Vadot soc { 65*354d7675SEmmanuel Vadot #address-cells = <2>; 66*354d7675SEmmanuel Vadot #size-cells = <2>; 67*354d7675SEmmanuel Vadot pcie_phy: pcie-phy@fc000000 { 68*354d7675SEmmanuel Vadot compatible = "hisilicon,hi970-pcie-phy"; 69*354d7675SEmmanuel Vadot reg = <0x0 0xfc000000 0x0 0x80000>; 70*354d7675SEmmanuel Vadot #phy-cells = <0>; 71*354d7675SEmmanuel Vadot phy-supply = <&ldo33>; 72*354d7675SEmmanuel Vadot clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, 73*354d7675SEmmanuel Vadot <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, 74*354d7675SEmmanuel Vadot <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, 75*354d7675SEmmanuel Vadot <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, 76*354d7675SEmmanuel Vadot <&crg_ctrl HI3670_ACLK_GATE_PCIE>; 77*354d7675SEmmanuel Vadot clock-names = "phy_ref", "aux", 78*354d7675SEmmanuel Vadot "apb_phy", "apb_sys", "aclk"; 79*354d7675SEmmanuel Vadot hisilicon,eye-diagram-param = <0xffffffff 0xffffffff 80*354d7675SEmmanuel Vadot 0xffffffff 0xffffffff 0xffffffff>; 81*354d7675SEmmanuel Vadot }; 82*354d7675SEmmanuel Vadot }; 83