xref: /freebsd/sys/contrib/device-tree/Bindings/pci/rockchip-dw-pcie.yaml (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: DesignWare based PCIe controller on Rockchip SoCs
8
9maintainers:
10  - Shawn Lin <shawn.lin@rock-chips.com>
11  - Simon Xue <xxm@rock-chips.com>
12  - Heiko Stuebner <heiko@sntech.de>
13
14description: |+
15  RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16  PCIe IP and thus inherits all the common properties defined in
17  designware-pcie.txt.
18
19allOf:
20  - $ref: /schemas/pci/pci-bus.yaml#
21
22# We need a select here so we don't match all nodes with 'snps,dw-pcie'
23select:
24  properties:
25    compatible:
26      contains:
27        const: rockchip,rk3568-pcie
28  required:
29    - compatible
30
31properties:
32  compatible:
33    items:
34      - const: rockchip,rk3568-pcie
35      - const: snps,dw-pcie
36
37  reg:
38    items:
39      - description: Data Bus Interface (DBI) registers
40      - description: Rockchip designed configuration registers
41      - description: Config registers
42
43  reg-names:
44    items:
45      - const: dbi
46      - const: apb
47      - const: config
48
49  clocks:
50    items:
51      - description: AHB clock for PCIe master
52      - description: AHB clock for PCIe slave
53      - description: AHB clock for PCIe dbi
54      - description: APB clock for PCIe
55      - description: Auxiliary clock for PCIe
56
57  clock-names:
58    items:
59      - const: aclk_mst
60      - const: aclk_slv
61      - const: aclk_dbi
62      - const: pclk
63      - const: aux
64
65  msi-map: true
66
67  num-lanes: true
68
69  phys:
70    maxItems: 1
71
72  phy-names:
73    const: pcie-phy
74
75  power-domains:
76    maxItems: 1
77
78  ranges:
79    maxItems: 2
80
81  resets:
82    maxItems: 1
83
84  reset-names:
85    const: pipe
86
87  vpcie3v3-supply: true
88
89required:
90  - compatible
91  - reg
92  - reg-names
93  - clocks
94  - clock-names
95  - msi-map
96  - num-lanes
97  - phys
98  - phy-names
99  - power-domains
100  - resets
101  - reset-names
102
103unevaluatedProperties: false
104
105examples:
106  - |
107
108    bus {
109        #address-cells = <2>;
110        #size-cells = <2>;
111
112        pcie3x2: pcie@fe280000 {
113            compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
114            reg = <0x3 0xc0800000 0x0 0x390000>,
115                  <0x0 0xfe280000 0x0 0x10000>,
116                  <0x3 0x80000000 0x0 0x100000>;
117            reg-names = "dbi", "apb", "config";
118            bus-range = <0x20 0x2f>;
119            clocks = <&cru 143>, <&cru 144>,
120                     <&cru 145>, <&cru 146>,
121                     <&cru 147>;
122            clock-names = "aclk_mst", "aclk_slv",
123                          "aclk_dbi", "pclk",
124                          "aux";
125            device_type = "pci";
126            linux,pci-domain = <2>;
127            max-link-speed = <2>;
128            msi-map = <0x2000 &its 0x2000 0x1000>;
129            num-lanes = <2>;
130            phys = <&pcie30phy>;
131            phy-names = "pcie-phy";
132            power-domains = <&power 15>;
133            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
134                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
135            resets = <&cru 193>;
136            reset-names = "pipe";
137            #address-cells = <3>;
138            #size-cells = <2>;
139        };
140    };
141...
142