1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/fsl,fec.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Fast Ethernet Controller (FEC) 8 9maintainers: 10 - Joakim Zhang <qiangqing.zhang@nxp.com> 11 12allOf: 13 - $ref: ethernet-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - enum: 19 - fsl,imx25-fec 20 - fsl,imx27-fec 21 - fsl,imx28-fec 22 - fsl,imx6q-fec 23 - fsl,mvf600-fec 24 - items: 25 - enum: 26 - fsl,imx53-fec 27 - fsl,imx6sl-fec 28 - const: fsl,imx25-fec 29 - items: 30 - enum: 31 - fsl,imx35-fec 32 - fsl,imx51-fec 33 - const: fsl,imx27-fec 34 - items: 35 - enum: 36 - fsl,imx6ul-fec 37 - fsl,imx6sx-fec 38 - const: fsl,imx6q-fec 39 - items: 40 - enum: 41 - fsl,imx7d-fec 42 - const: fsl,imx6sx-fec 43 - items: 44 - const: fsl,imx8mq-fec 45 - const: fsl,imx6sx-fec 46 - items: 47 - enum: 48 - fsl,imx8mm-fec 49 - fsl,imx8mn-fec 50 - fsl,imx8mp-fec 51 - const: fsl,imx8mq-fec 52 - const: fsl,imx6sx-fec 53 - items: 54 - const: fsl,imx8qm-fec 55 - const: fsl,imx6sx-fec 56 - items: 57 - enum: 58 - fsl,imx8qxp-fec 59 - const: fsl,imx8qm-fec 60 - const: fsl,imx6sx-fec 61 - items: 62 - enum: 63 - fsl,imx8ulp-fec 64 - const: fsl,imx6ul-fec 65 - const: fsl,imx6q-fec 66 67 reg: 68 maxItems: 1 69 70 interrupts: 71 minItems: 1 72 maxItems: 4 73 74 interrupt-names: 75 oneOf: 76 - items: 77 - const: int0 78 - items: 79 - const: int0 80 - const: pps 81 - items: 82 - const: int0 83 - const: int1 84 - const: int2 85 - items: 86 - const: int0 87 - const: int1 88 - const: int2 89 - const: pps 90 91 clocks: 92 minItems: 2 93 maxItems: 5 94 description: 95 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. 96 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. 97 The "ptp"(option), for IEEE1588 timer clock that requires the clock. 98 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like 99 RGMII TXC clock or RMII reference clock. It depends on board design, 100 the clock is required if RGMII TXC and RMII reference clock source from 101 SOC internal PLL. 102 The "enet_out"(option), output clock for external device, like supply clock 103 for PHY. The clock is required if PHY clock source from SOC. 104 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. 105 The clock is required if SoC RGMII enable clock delay. 106 107 clock-names: 108 minItems: 2 109 maxItems: 5 110 items: 111 enum: 112 - ipg 113 - ahb 114 - ptp 115 - enet_clk_ref 116 - enet_out 117 - enet_2x_txclk 118 119 phy-mode: true 120 121 phy-handle: true 122 123 fixed-link: true 124 125 local-mac-address: true 126 127 mac-address: true 128 129 nvmem-cells: true 130 131 nvmem-cell-names: true 132 133 tx-internal-delay-ps: 134 enum: [0, 2000] 135 136 rx-internal-delay-ps: 137 enum: [0, 2000] 138 139 phy-supply: 140 description: 141 Regulator that powers the Ethernet PHY. 142 143 fsl,num-tx-queues: 144 $ref: /schemas/types.yaml#/definitions/uint32 145 description: 146 The property is valid for enet-avb IP, which supports hw multi queues. 147 Should specify the tx queue number, otherwise set tx queue number to 1. 148 enum: [1, 2, 3] 149 150 fsl,num-rx-queues: 151 $ref: /schemas/types.yaml#/definitions/uint32 152 description: 153 The property is valid for enet-avb IP, which supports hw multi queues. 154 Should specify the rx queue number, otherwise set rx queue number to 1. 155 enum: [1, 2, 3] 156 157 fsl,magic-packet: 158 $ref: /schemas/types.yaml#/definitions/flag 159 description: 160 If present, indicates that the hardware supports waking up via magic packet. 161 162 fsl,err006687-workaround-present: 163 $ref: /schemas/types.yaml#/definitions/flag 164 description: 165 If present indicates that the system has the hardware workaround for 166 ERR006687 applied and does not need a software workaround. 167 168 fsl,stop-mode: 169 $ref: /schemas/types.yaml#/definitions/phandle-array 170 items: 171 - items: 172 - description: phandle to general purpose register node 173 - description: the gpr register offset for ENET stop request 174 - description: the gpr bit offset for ENET stop request 175 description: 176 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. 177 178 mdio: 179 $ref: mdio.yaml# 180 unevaluatedProperties: false 181 description: 182 Specifies the mdio bus in the FEC, used as a container for phy nodes. 183 184 # Deprecated optional properties: 185 # To avoid these, create a phy node according to ethernet-phy.yaml in the same 186 # directory, and point the FEC's "phy-handle" property to it. Then use 187 # the phy's reset binding, again described by ethernet-phy.yaml. 188 189 phy-reset-gpios: 190 deprecated: true 191 description: 192 Should specify the gpio for phy reset. 193 194 phy-reset-duration: 195 $ref: /schemas/types.yaml#/definitions/uint32 196 deprecated: true 197 description: 198 Reset duration in milliseconds. Should present only if property 199 "phy-reset-gpios" is available. Missing the property will have the 200 duration be 1 millisecond. Numbers greater than 1000 are invalid 201 and 1 millisecond will be used instead. 202 203 phy-reset-active-high: 204 type: boolean 205 deprecated: true 206 description: 207 If present then the reset sequence using the GPIO specified in the 208 "phy-reset-gpios" property is reversed (H=reset state, L=operation state). 209 210 phy-reset-post-delay: 211 $ref: /schemas/types.yaml#/definitions/uint32 212 deprecated: true 213 description: 214 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay 215 milliseconds will be observed after the phy-reset-gpios has been toggled. 216 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. 217 Other delays are invalid. 218 219required: 220 - compatible 221 - reg 222 - interrupts 223 224# FIXME: We had better set additionalProperties to false to avoid invalid or at 225# least undocumented properties. However, PHY may have a deprecated option to 226# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find 227# these boards which is based on i.MX6QDL. 228unevaluatedProperties: false 229 230examples: 231 - | 232 ethernet@83fec000 { 233 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 234 reg = <0x83fec000 0x4000>; 235 interrupts = <87>; 236 phy-mode = "mii"; 237 phy-reset-gpios = <&gpio2 14 0>; 238 phy-supply = <®_fec_supply>; 239 }; 240 241 ethernet@83fed000 { 242 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 243 reg = <0x83fed000 0x4000>; 244 interrupts = <87>; 245 phy-mode = "mii"; 246 phy-reset-gpios = <&gpio2 14 0>; 247 phy-supply = <®_fec_supply>; 248 phy-handle = <ðphy0>; 249 250 mdio { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 254 ethphy0: ethernet-phy@0 { 255 compatible = "ethernet-phy-ieee802.3-c22"; 256 reg = <0>; 257 }; 258 }; 259 }; 260