1Realtek SMI-based Switches 2========================== 3 4The SMI "Simple Management Interface" is a two-wire protocol using 5bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does 6not use the MDIO protocol. This binding defines how to specify the 7SMI-based Realtek devices. 8 9Required properties: 10 11- compatible: must be exactly one of: 12 "realtek,rtl8365mb" (4+1 ports) 13 "realtek,rtl8366" 14 "realtek,rtl8366rb" (4+1 ports) 15 "realtek,rtl8366s" (4+1 ports) 16 "realtek,rtl8367" 17 "realtek,rtl8367b" 18 "realtek,rtl8368s" (8 port) 19 "realtek,rtl8369" 20 "realtek,rtl8370" (8 port) 21 22Required properties: 23- mdc-gpios: GPIO line for the MDC clock line. 24- mdio-gpios: GPIO line for the MDIO data line. 25- reset-gpios: GPIO line for the reset signal. 26 27Optional properties: 28- realtek,disable-leds: if the LED drivers are not used in the 29 hardware design this will disable them so they are not turned on 30 and wasting power. 31 32Required subnodes: 33 34- interrupt-controller 35 36 This defines an interrupt controller with an IRQ line (typically 37 a GPIO) that will demultiplex and handle the interrupt from the single 38 interrupt line coming out of one of the SMI-based chips. It most 39 importantly provides link up/down interrupts to the PHY blocks inside 40 the ASIC. 41 42Required properties of interrupt-controller: 43 44- interrupt: parent interrupt, see interrupt-controller/interrupts.txt 45- interrupt-controller: see interrupt-controller/interrupts.txt 46- #address-cells: should be <0> 47- #interrupt-cells: should be <1> 48 49- mdio 50 51 This defines the internal MDIO bus of the SMI device, mostly for the 52 purpose of being able to hook the interrupts to the right PHY and 53 the right PHY to the corresponding port. 54 55Required properties of mdio: 56 57- compatible: should be set to "realtek,smi-mdio" for all SMI devices 58 59See net/mdio.txt for additional MDIO bus properties. 60 61See net/dsa/dsa.txt for a list of additional required and optional properties 62and subnodes of DSA switches. 63 64Examples: 65 66An example for the RTL8366RB: 67 68switch { 69 compatible = "realtek,rtl8366rb"; 70 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ 71 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; 72 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; 73 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 74 75 switch_intc: interrupt-controller { 76 /* GPIO 15 provides the interrupt */ 77 interrupt-parent = <&gpio0>; 78 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 79 interrupt-controller; 80 #address-cells = <0>; 81 #interrupt-cells = <1>; 82 }; 83 84 ports { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 reg = <0>; 88 port@0 { 89 reg = <0>; 90 label = "lan0"; 91 phy-handle = <&phy0>; 92 }; 93 port@1 { 94 reg = <1>; 95 label = "lan1"; 96 phy-handle = <&phy1>; 97 }; 98 port@2 { 99 reg = <2>; 100 label = "lan2"; 101 phy-handle = <&phy2>; 102 }; 103 port@3 { 104 reg = <3>; 105 label = "lan3"; 106 phy-handle = <&phy3>; 107 }; 108 port@4 { 109 reg = <4>; 110 label = "wan"; 111 phy-handle = <&phy4>; 112 }; 113 port@5 { 114 reg = <5>; 115 label = "cpu"; 116 ethernet = <&gmac0>; 117 phy-mode = "rgmii"; 118 fixed-link { 119 speed = <1000>; 120 full-duplex; 121 }; 122 }; 123 }; 124 125 mdio { 126 compatible = "realtek,smi-mdio", "dsa-mdio"; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 phy0: phy@0 { 131 reg = <0>; 132 interrupt-parent = <&switch_intc>; 133 interrupts = <0>; 134 }; 135 phy1: phy@1 { 136 reg = <1>; 137 interrupt-parent = <&switch_intc>; 138 interrupts = <1>; 139 }; 140 phy2: phy@2 { 141 reg = <2>; 142 interrupt-parent = <&switch_intc>; 143 interrupts = <2>; 144 }; 145 phy3: phy@3 { 146 reg = <3>; 147 interrupt-parent = <&switch_intc>; 148 interrupts = <3>; 149 }; 150 phy4: phy@4 { 151 reg = <4>; 152 interrupt-parent = <&switch_intc>; 153 interrupts = <12>; 154 }; 155 }; 156}; 157 158An example for the RTL8365MB-VC: 159 160switch { 161 compatible = "realtek,rtl8365mb"; 162 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; 163 mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 164 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 165 166 switch_intc: interrupt-controller { 167 interrupt-parent = <&gpio5>; 168 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 169 interrupt-controller; 170 #address-cells = <0>; 171 #interrupt-cells = <1>; 172 }; 173 174 ports { 175 #address-cells = <1>; 176 #size-cells = <0>; 177 reg = <0>; 178 port@0 { 179 reg = <0>; 180 label = "swp0"; 181 phy-handle = <ðphy0>; 182 }; 183 port@1 { 184 reg = <1>; 185 label = "swp1"; 186 phy-handle = <ðphy1>; 187 }; 188 port@2 { 189 reg = <2>; 190 label = "swp2"; 191 phy-handle = <ðphy2>; 192 }; 193 port@3 { 194 reg = <3>; 195 label = "swp3"; 196 phy-handle = <ðphy3>; 197 }; 198 port@6 { 199 reg = <6>; 200 label = "cpu"; 201 ethernet = <&fec1>; 202 phy-mode = "rgmii"; 203 tx-internal-delay-ps = <2000>; 204 rx-internal-delay-ps = <2000>; 205 206 fixed-link { 207 speed = <1000>; 208 full-duplex; 209 pause; 210 }; 211 }; 212 }; 213 214 mdio { 215 compatible = "realtek,smi-mdio"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 ethphy0: phy@0 { 220 reg = <0>; 221 interrupt-parent = <&switch_intc>; 222 interrupts = <0>; 223 }; 224 ethphy1: phy@1 { 225 reg = <1>; 226 interrupt-parent = <&switch_intc>; 227 interrupts = <1>; 228 }; 229 ethphy2: phy@2 { 230 reg = <2>; 231 interrupt-parent = <&switch_intc>; 232 interrupts = <2>; 233 }; 234 ethphy3: phy@3 { 235 reg = <3>; 236 interrupt-parent = <&switch_intc>; 237 interrupts = <3>; 238 }; 239 }; 240}; 241