1Device tree bindings for NOR flash connect to TI GPMC 2 3NOR flash connected to the TI GPMC (found on OMAP boards) are represented as 4child nodes of the GPMC controller with a name of "nor". 5 6All timing relevant properties as well as generic GPMC child properties are 7explained in a separate documents. Please refer to 8Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 9 10Required properties: 11- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and 12 16-bit devices and so must be either 1 or 2 bytes. 13- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml 14- gpmc,cs-on-ns: Chip-select assertion time 15- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads 16- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes 17- gpmc,oe-on-ns: Output-enable assertion time 18- gpmc,oe-off-ns: Output-enable de-assertion time 19- gpmc,we-on-ns Write-enable assertion time 20- gpmc,we-off-ns: Write-enable de-assertion time 21- gpmc,access-ns: Start cycle to first data capture (read access) 22- gpmc,rd-cycle-ns: Total read cycle time 23- gpmc,wr-cycle-ns: Total write cycle time 24- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml 25- reg: Chip-select, base address (relative to chip-select) 26 and size of NOR flash. Note that base address will be 27 typically 0 as this is the start of the chip-select. 28 29Optional properties: 30- gpmc,XXX Additional GPMC timings and settings parameters. See 31 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 32 33Optional properties for partition table parsing: 34- #address-cells: should be set to 1 35- #size-cells: should be set to 1 36 37Example: 38 39gpmc: gpmc@6e000000 { 40 compatible = "ti,omap3430-gpmc", "simple-bus"; 41 ti,hwmods = "gpmc"; 42 reg = <0x6e000000 0x1000>; 43 interrupts = <20>; 44 gpmc,num-cs = <8>; 45 gpmc,num-waitpins = <4>; 46 #address-cells = <2>; 47 #size-cells = <1>; 48 49 ranges = <0 0 0x10000000 0x08000000>; 50 51 nor@0,0 { 52 compatible = "cfi-flash"; 53 linux,mtd-name= "intel,pf48f6000m0y1be"; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 reg = <0 0 0x08000000>; 57 bank-width = <2>; 58 59 gpmc,mux-add-data; 60 gpmc,cs-on-ns = <0>; 61 gpmc,cs-rd-off-ns = <186>; 62 gpmc,cs-wr-off-ns = <186>; 63 gpmc,adv-on-ns = <12>; 64 gpmc,adv-rd-off-ns = <48>; 65 gpmc,adv-wr-off-ns = <48>; 66 gpmc,oe-on-ns = <54>; 67 gpmc,oe-off-ns = <168>; 68 gpmc,we-on-ns = <54>; 69 gpmc,we-off-ns = <168>; 70 gpmc,rd-cycle-ns = <186>; 71 gpmc,wr-cycle-ns = <186>; 72 gpmc,access-ns = <114>; 73 gpmc,page-burst-access-ns = <6>; 74 gpmc,bus-turnaround-ns = <12>; 75 gpmc,cycle2cycle-delay-ns = <18>; 76 gpmc,wr-data-mux-bus-ns = <90>; 77 gpmc,wr-access-ns = <186>; 78 gpmc,cycle2cycle-samecsen; 79 gpmc,cycle2cycle-diffcsen; 80 81 partition@0 { 82 label = "bootloader-nor"; 83 reg = <0 0x40000>; 84 }; 85 partition@40000 { 86 label = "params-nor"; 87 reg = <0x40000 0x40000>; 88 }; 89 partition@80000 { 90 label = "kernel-nor"; 91 reg = <0x80000 0x200000>; 92 }; 93 partition@280000 { 94 label = "filesystem-nor"; 95 reg = <0x240000 0x7d80000>; 96 }; 97 }; 98}; 99