1SMI (Smart Multimedia Interface) Common 2 3The hardware block diagram please check bindings/iommu/mediatek,iommu.txt 4 5Mediatek SMI have two generations of HW architecture, here is the list 6which generation the SoCs use: 7generation 1: mt2701 and mt7623. 8generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183. 9 10There's slight differences between the two SMI, for generation 2, the 11register which control the iommu port is at each larb's register base. But 12for generation 1, the register is at smi ao base(smi always on register 13base). Besides that, the smi async clock should be prepared and enabled for 14SMI generation 1 to transform the smi clock into emi clock domain, but that is 15not needed for SMI generation 2. 16 17Required properties: 18- compatible : must be one of : 19 "mediatek,mt2701-smi-common" 20 "mediatek,mt2712-smi-common" 21 "mediatek,mt6779-smi-common" 22 "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" 23 "mediatek,mt8167-smi-common" 24 "mediatek,mt8173-smi-common" 25 "mediatek,mt8183-smi-common" 26- reg : the register and size of the SMI block. 27- power-domains : a phandle to the power domain of this local arbiter. 28- clocks : Must contain an entry for each entry in clock-names. 29- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries 30 for generation 2 smi HW as follows: 31 - "apb" : Advanced Peripheral Bus clock, It's the clock for setting 32 the register. 33 - "smi" : It's the clock for transfer data and command. 34 They may be the same if both source clocks are the same. 35 - "async" : asynchronous clock, it help transform the smi clock into the emi 36 clock domain, this clock is only needed by generation 1 smi HW. 37 and these 2 option clocks for generation 2 smi HW: 38 - "gals0": the path0 clock of GALS(Global Async Local Sync). 39 - "gals1": the path1 clock of GALS(Global Async Local Sync). 40 Here is the list which has this GALS: mt6779 and mt8183. 41 42Example: 43 smi_common: smi@14022000 { 44 compatible = "mediatek,mt8173-smi-common"; 45 reg = <0 0x14022000 0 0x1000>; 46 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 47 clocks = <&mmsys CLK_MM_SMI_COMMON>, 48 <&mmsys CLK_MM_SMI_COMMON>; 49 clock-names = "apb", "smi"; 50 }; 51