1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) 2022 Renesas Electronics Corp. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing 9 10maintainers: 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12 13description: 14 The CRU image processing module is a data conversion module equipped with pixel 15 color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and 16 parallel (including ITU-R BT.656) input are provided as the image sensor interface. 17 18properties: 19 compatible: 20 items: 21 - enum: 22 - renesas,r9a07g044-cru # RZ/G2{L,LC} 23 - renesas,r9a07g054-cru # RZ/V2L 24 - const: renesas,rzg2l-cru 25 26 reg: 27 maxItems: 1 28 29 interrupts: 30 maxItems: 3 31 32 interrupt-names: 33 items: 34 - const: image_conv 35 - const: image_conv_err 36 - const: axi_mst_err 37 38 clocks: 39 items: 40 - description: CRU Main clock 41 - description: CRU Register access clock 42 - description: CRU image transfer clock 43 44 clock-names: 45 items: 46 - const: video 47 - const: apb 48 - const: axi 49 50 power-domains: 51 maxItems: 1 52 53 resets: 54 items: 55 - description: CRU_PRESETN reset terminal 56 - description: CRU_ARESETN reset terminal 57 58 reset-names: 59 items: 60 - const: presetn 61 - const: aresetn 62 63 ports: 64 $ref: /schemas/graph.yaml#/properties/ports 65 66 properties: 67 port@0: 68 $ref: /schemas/graph.yaml#/$defs/port-base 69 unevaluatedProperties: false 70 description: 71 Input port node, single endpoint describing a parallel input source. 72 73 properties: 74 endpoint: 75 $ref: video-interfaces.yaml# 76 unevaluatedProperties: false 77 78 properties: 79 hsync-active: true 80 vsync-active: true 81 bus-width: true 82 data-shift: true 83 84 port@1: 85 $ref: /schemas/graph.yaml#/properties/port 86 description: 87 Input port node, describing the Image Processing module connected to the 88 CSI-2 receiver. 89 90 required: 91 - port@0 92 - port@1 93 94required: 95 - compatible 96 - reg 97 - interrupts 98 - interrupt-names 99 - clocks 100 - clock-names 101 - resets 102 - reset-names 103 - power-domains 104 105additionalProperties: false 106 107examples: 108 # Device node example with CSI-2 109 - | 110 #include <dt-bindings/clock/r9a07g044-cpg.h> 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 112 113 cru: video@10830000 { 114 compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; 115 reg = <0x10830000 0x400>; 116 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; 120 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, 121 <&cpg CPG_MOD R9A07G044_CRU_PCLK>, 122 <&cpg CPG_MOD R9A07G044_CRU_ACLK>; 123 clock-names = "video", "apb", "axi"; 124 power-domains = <&cpg>; 125 resets = <&cpg R9A07G044_CRU_PRESETN>, 126 <&cpg R9A07G044_CRU_ARESETN>; 127 reset-names = "presetn", "aresetn"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 port@0 { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 reg = <0>; 137 138 cru_parallel_in: endpoint@0 { 139 reg = <0>; 140 remote-endpoint = <&ov5642>; 141 hsync-active = <1>; 142 vsync-active = <1>; 143 }; 144 }; 145 146 port@1 { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 reg = <1>; 150 151 cru_csi_in: endpoint@0 { 152 reg = <0>; 153 remote-endpoint = <&csi_cru_in>; 154 }; 155 }; 156 }; 157 }; 158