1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Mediatek Video Decode Accelerator 9 10maintainers: 11 - Yunfei Dong <yunfei.dong@mediatek.com> 12 13description: |+ 14 Mediatek Video Decode is the video decode hardware present in Mediatek 15 SoCs which supports high resolution decoding functionalities. 16 17properties: 18 compatible: 19 enum: 20 - mediatek,mt8173-vcodec-dec 21 - mediatek,mt8183-vcodec-dec 22 23 reg: 24 maxItems: 12 25 26 interrupts: 27 maxItems: 1 28 29 clocks: 30 maxItems: 8 31 32 clock-names: 33 items: 34 - const: vcodecpll 35 - const: univpll_d2 36 - const: clk_cci400_sel 37 - const: vdec_sel 38 - const: vdecpll 39 - const: vencpll 40 - const: venc_lt_sel 41 - const: vdec_bus_clk_src 42 43 assigned-clocks: true 44 45 assigned-clock-parents: true 46 47 assigned-clock-rates: true 48 49 power-domains: 50 maxItems: 1 51 52 iommus: 53 minItems: 1 54 maxItems: 32 55 description: | 56 List of the hardware port in respective IOMMU block for current Socs. 57 Refer to bindings/iommu/mediatek,iommu.yaml. 58 59 mediatek,vpu: 60 $ref: /schemas/types.yaml#/definitions/phandle 61 description: 62 Describes point to vpu. 63 64 mediatek,scp: 65 $ref: /schemas/types.yaml#/definitions/phandle 66 description: 67 Describes point to scp. 68 69required: 70 - compatible 71 - reg 72 - interrupts 73 - clocks 74 - clock-names 75 - iommus 76 - assigned-clocks 77 - assigned-clock-parents 78 79allOf: 80 - if: 81 properties: 82 compatible: 83 contains: 84 enum: 85 - mediatek,mt8183-vcodec-dec 86 87 then: 88 required: 89 - mediatek,scp 90 91 - if: 92 properties: 93 compatible: 94 contains: 95 enum: 96 - mediatek,mt8173-vcodec-dec 97 98 then: 99 required: 100 - mediatek,vpu 101 102additionalProperties: false 103 104examples: 105 - | 106 #include <dt-bindings/interrupt-controller/arm-gic.h> 107 #include <dt-bindings/clock/mt8173-clk.h> 108 #include <dt-bindings/memory/mt8173-larb-port.h> 109 #include <dt-bindings/interrupt-controller/irq.h> 110 #include <dt-bindings/power/mt8173-power.h> 111 112 vcodec_dec: vcodec@16000000 { 113 compatible = "mediatek,mt8173-vcodec-dec"; 114 reg = <0x16000000 0x100>, /*VDEC_SYS*/ 115 <0x16020000 0x1000>, /*VDEC_MISC*/ 116 <0x16021000 0x800>, /*VDEC_LD*/ 117 <0x16021800 0x800>, /*VDEC_TOP*/ 118 <0x16022000 0x1000>, /*VDEC_CM*/ 119 <0x16023000 0x1000>, /*VDEC_AD*/ 120 <0x16024000 0x1000>, /*VDEC_AV*/ 121 <0x16025000 0x1000>, /*VDEC_PP*/ 122 <0x16026800 0x800>, /*VP8_VD*/ 123 <0x16027000 0x800>, /*VP6_VD*/ 124 <0x16027800 0x800>, /*VP8_VL*/ 125 <0x16028400 0x400>; /*VP9_VD*/ 126 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 127 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 128 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 129 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 130 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 131 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 132 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 133 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 134 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 135 mediatek,vpu = <&vpu>; 136 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 137 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 138 <&topckgen CLK_TOP_UNIVPLL_D2>, 139 <&topckgen CLK_TOP_CCI400_SEL>, 140 <&topckgen CLK_TOP_VDEC_SEL>, 141 <&topckgen CLK_TOP_VCODECPLL>, 142 <&apmixedsys CLK_APMIXED_VENCPLL>, 143 <&topckgen CLK_TOP_VENC_LT_SEL>, 144 <&topckgen CLK_TOP_VCODECPLL_370P5>; 145 clock-names = "vcodecpll", 146 "univpll_d2", 147 "clk_cci400_sel", 148 "vdec_sel", 149 "vdecpll", 150 "vencpll", 151 "venc_lt_sel", 152 "vdec_bus_clk_src"; 153 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 154 <&topckgen CLK_TOP_CCI400_SEL>, 155 <&topckgen CLK_TOP_VDEC_SEL>, 156 <&apmixedsys CLK_APMIXED_VCODECPLL>, 157 <&apmixedsys CLK_APMIXED_VENCPLL>; 158 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 159 <&topckgen CLK_TOP_UNIVPLL_D2>, 160 <&topckgen CLK_TOP_VCODECPLL>; 161 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 162 }; 163