1* QCOM IOMMU 2 3The MSM IOMMU is an implementation compatible with the ARM VMSA short 4descriptor page tables. It provides address translation for bus masters outside 5of the CPU, each connected to the IOMMU through a port called micro-TLB. 6 7Required Properties: 8 9 - compatible: Must contain "qcom,apq8064-iommu". 10 - reg: Base address and size of the IOMMU registers. 11 - interrupts: Specifiers for the MMU fault interrupts. For instances that 12 support secure mode two interrupts must be specified, for non-secure and 13 secure mode, in that order. For instances that don't support secure mode a 14 single interrupt must be specified. 15 - #iommu-cells: The number of cells needed to specify the stream id. This 16 is always 1. 17 - qcom,ncb: The total number of context banks in the IOMMU. 18 - clocks : List of clocks to be used during SMMU register access. See 19 Documentation/devicetree/bindings/clock/clock-bindings.txt 20 for information about the format. For each clock specified 21 here, there must be a corresponding entry in clock-names 22 (see below). 23 24 - clock-names : List of clock names corresponding to the clocks specified in 25 the "clocks" property (above). 26 Should be "smmu_pclk" for specifying the interface clock 27 required for iommu's register accesses. 28 Should be "smmu_clk" for specifying the functional clock 29 required by iommu for bus accesses. 30 31Each bus master connected to an IOMMU must reference the IOMMU in its device 32node with the following property: 33 34 - iommus: A reference to the IOMMU in multiple cells. The first cell is a 35 phandle to the IOMMU and the second cell is the stream id. 36 A single master device can be connected to more than one iommu 37 and multiple contexts in each of the iommu. So multiple entries 38 are required to list all the iommus and the stream ids that the 39 master is connected to. 40 41Example: mdp iommu and its bus master 42 43 mdp_port0: iommu@7500000 { 44 compatible = "qcom,apq8064-iommu"; 45 #iommu-cells = <1>; 46 clock-names = 47 "smmu_pclk", 48 "smmu_clk"; 49 clocks = 50 <&mmcc SMMU_AHB_CLK>, 51 <&mmcc MDP_AXI_CLK>; 52 reg = <0x07500000 0x100000>; 53 interrupts = 54 <GIC_SPI 63 0>, 55 <GIC_SPI 64 0>; 56 qcom,ncb = <2>; 57 }; 58 59 mdp: qcom,mdp@5100000 { 60 compatible = "qcom,mdp"; 61 ... 62 iommus = <&mdp_port0 0 63 &mdp_port0 2>; 64 }; 65