1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - const: qcom,smmu-v2 32 33 - description: Qcom SoCs implementing "arm,mmu-500" 34 items: 35 - enum: 36 - qcom,sc7180-smmu-500 37 - qcom,sc7280-smmu-500 38 - qcom,sc8180x-smmu-500 39 - qcom,sdm845-smmu-500 40 - qcom,sm8150-smmu-500 41 - qcom,sm8250-smmu-500 42 - qcom,sm8350-smmu-500 43 - const: arm,mmu-500 44 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 45 items: 46 - enum: 47 - qcom,sc7180-smmu-v2 48 - qcom,sdm845-smmu-v2 49 - const: qcom,adreno-smmu 50 - const: qcom,smmu-v2 51 - description: Marvell SoCs implementing "arm,mmu-500" 52 items: 53 - const: marvell,ap806-smmu-500 54 - const: arm,mmu-500 55 - description: NVIDIA SoCs that program two ARM MMU-500s identically 56 items: 57 - enum: 58 - nvidia,tegra194-smmu 59 - const: nvidia,smmu-500 60 - items: 61 - const: arm,mmu-500 62 - const: arm,smmu-v2 63 - items: 64 - enum: 65 - arm,mmu-400 66 - arm,mmu-401 67 - const: arm,smmu-v1 68 - enum: 69 - arm,smmu-v1 70 - arm,smmu-v2 71 - arm,mmu-400 72 - arm,mmu-401 73 - arm,mmu-500 74 - cavium,smmu-v2 75 76 reg: 77 minItems: 1 78 maxItems: 2 79 80 '#global-interrupts': 81 description: The number of global interrupts exposed by the device. 82 $ref: /schemas/types.yaml#/definitions/uint32 83 minimum: 0 84 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 85 86 '#iommu-cells': 87 enum: [ 1, 2 ] 88 description: | 89 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 90 value of 1, each IOMMU specifier represents a distinct stream ID emitted 91 by that device into the relevant SMMU. 92 93 SMMUs with stream matching support and complex masters may use a value of 94 2, where the second cell of the IOMMU specifier represents an SMR mask to 95 combine with the ID in the first cell. Care must be taken to ensure the 96 set of matched IDs does not result in conflicts. 97 98 interrupts: 99 minItems: 1 100 maxItems: 388 # 260 plus 128 contexts 101 description: | 102 Interrupt list, with the first #global-interrupts entries corresponding to 103 the global interrupts and any following entries corresponding to context 104 interrupts, specified in order of their indexing by the SMMU. 105 106 For SMMUv2 implementations, there must be exactly one interrupt per 107 context bank. In the case of a single, combined interrupt, it must be 108 listed multiple times. 109 110 dma-coherent: 111 description: | 112 Present if page table walks made by the SMMU are cache coherent with the 113 CPU. 114 115 NOTE: this only applies to the SMMU itself, not masters connected 116 upstream of the SMMU. 117 118 calxeda,smmu-secure-config-access: 119 type: boolean 120 description: 121 Enable proper handling of buggy implementations that always use secure 122 access to SMMU configuration registers. In this case non-secure aliases of 123 secure registers have to be used during SMMU configuration. 124 125 stream-match-mask: 126 $ref: /schemas/types.yaml#/definitions/uint32 127 description: | 128 For SMMUs supporting stream matching and using #iommu-cells = <1>, 129 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 130 be programmed into the SMRn.MASK field of every stream match register 131 used). For cases where it is desirable to ignore some portion of every 132 Stream ID (e.g. for certain MMU-500 configurations given globally unique 133 input IDs). This property is not valid for SMMUs using stream indexing, or 134 using stream matching with #iommu-cells = <2>, and may be ignored if 135 present in such cases. 136 137 clock-names: 138 items: 139 - const: bus 140 - const: iface 141 142 clocks: 143 items: 144 - description: bus clock required for downstream bus access and for the 145 smmu ptw 146 - description: interface clock required to access smmu's registers 147 through the TCU's programming interface. 148 149 power-domains: 150 maxItems: 1 151 152required: 153 - compatible 154 - reg 155 - '#global-interrupts' 156 - '#iommu-cells' 157 - interrupts 158 159additionalProperties: false 160 161allOf: 162 - if: 163 properties: 164 compatible: 165 contains: 166 enum: 167 - nvidia,tegra194-smmu 168 then: 169 properties: 170 reg: 171 minItems: 2 172 maxItems: 2 173 else: 174 properties: 175 reg: 176 maxItems: 1 177 178examples: 179 - |+ 180 /* SMMU with stream matching or stream indexing */ 181 smmu1: iommu@ba5e0000 { 182 compatible = "arm,smmu-v1"; 183 reg = <0xba5e0000 0x10000>; 184 #global-interrupts = <2>; 185 interrupts = <0 32 4>, 186 <0 33 4>, 187 <0 34 4>, /* This is the first context interrupt */ 188 <0 35 4>, 189 <0 36 4>, 190 <0 37 4>; 191 #iommu-cells = <1>; 192 }; 193 194 /* device with two stream IDs, 0 and 7 */ 195 master1 { 196 iommus = <&smmu1 0>, 197 <&smmu1 7>; 198 }; 199 200 201 /* SMMU with stream matching */ 202 smmu2: iommu@ba5f0000 { 203 compatible = "arm,smmu-v1"; 204 reg = <0xba5f0000 0x10000>; 205 #global-interrupts = <2>; 206 interrupts = <0 38 4>, 207 <0 39 4>, 208 <0 40 4>, /* This is the first context interrupt */ 209 <0 41 4>, 210 <0 42 4>, 211 <0 43 4>; 212 #iommu-cells = <2>; 213 }; 214 215 /* device with stream IDs 0 and 7 */ 216 master2 { 217 iommus = <&smmu2 0 0>, 218 <&smmu2 7 0>; 219 }; 220 221 /* device with stream IDs 1, 17, 33 and 49 */ 222 master3 { 223 iommus = <&smmu2 1 0x30>; 224 }; 225 226 227 /* ARM MMU-500 with 10-bit stream ID input configuration */ 228 smmu3: iommu@ba600000 { 229 compatible = "arm,mmu-500", "arm,smmu-v2"; 230 reg = <0xba600000 0x10000>; 231 #global-interrupts = <2>; 232 interrupts = <0 44 4>, 233 <0 45 4>, 234 <0 46 4>, /* This is the first context interrupt */ 235 <0 47 4>, 236 <0 48 4>, 237 <0 49 4>; 238 #iommu-cells = <1>; 239 /* always ignore appended 5-bit TBU number */ 240 stream-match-mask = <0x7c00>; 241 }; 242 243 bus { 244 /* bus whose child devices emit one unique 10-bit stream 245 ID each, but may master through multiple SMMU TBUs */ 246 iommu-map = <0 &smmu3 0 0x400>; 247 248 249 }; 250 251 - |+ 252 /* Qcom's arm,smmu-v2 implementation */ 253 #include <dt-bindings/interrupt-controller/arm-gic.h> 254 #include <dt-bindings/interrupt-controller/irq.h> 255 smmu4: iommu@d00000 { 256 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 257 reg = <0xd00000 0x10000>; 258 259 #global-interrupts = <1>; 260 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 263 #iommu-cells = <1>; 264 power-domains = <&mmcc 0>; 265 266 clocks = <&mmcc 123>, 267 <&mmcc 124>; 268 clock-names = "bus", "iface"; 269 }; 270