xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ti,sci-inta.txt (revision 5f4c09dd85bff675e0ca63c55ea3c517e0fddfcc) 
1Texas Instruments K3 Interrupt Aggregator
2=========================================
3
4The Interrupt Aggregator (INTA) provides a centralized machine
5which handles the termination of system events to that they can
6be coherently processed by the host(s) in the system. A maximum
7of 64 events can be mapped to a single interrupt.
8
9
10                              Interrupt Aggregator
11                     +-----------------------------------------+
12                     |      Intmap            VINT             |
13                     | +--------------+  +------------+        |
14            m ------>| | vint  | bit  |  | 0 |.....|63| vint0  |
15               .     | +--------------+  +------------+        |       +------+
16               .     |         .               .               |       | HOST |
17Globalevents  ------>|         .               .               |------>| IRQ  |
18               .     |         .               .               |       | CTRL |
19               .     |         .               .               |       +------+
20            n ------>| +--------------+  +------------+        |
21                     | | vint  | bit  |  | 0 |.....|63| vintx  |
22                     | +--------------+  +------------+        |
23                     |                                         |
24                     +-----------------------------------------+
25
26Configuration of these Intmap registers that maps global events to vint is done
27by a system controller (like the Device Memory and Security Controller on K3
28AM654 SoC). Driver should request the system controller to get the range
29of global events and vints assigned to the requesting host. Management
30of these requested resources should be handled by driver and requests
31system controller to map specific global event to vint, bit pair.
32
33Communication between the host processor running an OS and the system
34controller happens through a protocol called TI System Control Interface
35(TISCI protocol). For more details refer:
36Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
37
38TISCI Interrupt Aggregator Node:
39-------------------------------
40- compatible:		Must be "ti,sci-inta".
41- reg:			Should contain registers location and length.
42- interrupt-controller:	Identifies the node as an interrupt controller
43- msi-controller:	Identifies the node as an MSI controller.
44- interrupt-parent:	phandle of irq parent.
45- ti,sci:		Phandle to TI-SCI compatible System controller node.
46- ti,sci-dev-id:	TISCI device ID of the Interrupt Aggregator.
47- ti,sci-rm-range-vint:	Array of TISCI subtype ids representing vints(inta
48			outputs) range within this INTA, assigned to the
49			requesting host context.
50- ti,sci-rm-range-global-event:	Array of TISCI subtype ids representing the
51			global events range reaching this IA and are assigned
52			to the requesting host context.
53
54Example:
55--------
56main_udmass_inta: interrupt-controller@33d00000 {
57	compatible = "ti,sci-inta";
58	reg = <0x0 0x33d00000 0x0 0x100000>;
59	interrupt-controller;
60	msi-controller;
61	interrupt-parent = <&main_navss_intr>;
62	ti,sci = <&dmsc>;
63	ti,sci-dev-id = <179>;
64	ti,sci-rm-range-vint = <0x0>;
65	ti,sci-rm-range-global-event = <0x1>;
66};
67