xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ti,keystone-irq.yaml (revision ae5de77ed78ae54d86cead5604869212e8008e6b)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ti,keystone-irq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Keystone 2 IRQ controller IP

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>

description:
  On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ
  controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on
  HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx
  registers. This is one of the component used by the IPC mechanism used on
  Keystone SOCs.

properties:
  compatible:
    const: ti,keystone-irq

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 1

  interrupts:
    maxItems: 1

  ti,syscon-dev:
    description: Phandle and offset to syscon device
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to syscon device control registers
          - description: Offset to control register

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts
  - ti,syscon-dev

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    interrupt-controller@2a0 {
      compatible = "ti,keystone-irq";
      reg = <0x2a0 0x4>;
      ti,syscon-dev = <&devctrl 0x2a0>;
      interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
      interrupt-controller;
      #interrupt-cells = <1>;
    };