1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Mali Utgard GPU 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 - Maxime Ripard <mripard@kernel.org> 12 - Heiko Stuebner <heiko@sntech.de> 13 14properties: 15 $nodename: 16 pattern: '^gpu@[a-f0-9]+$' 17 compatible: 18 oneOf: 19 - items: 20 - const: allwinner,sun8i-a23-mali 21 - const: allwinner,sun7i-a20-mali 22 - const: arm,mali-400 23 - items: 24 - enum: 25 - allwinner,sun4i-a10-mali 26 - allwinner,sun7i-a20-mali 27 - allwinner,sun8i-h3-mali 28 - allwinner,sun8i-r40-mali 29 - allwinner,sun50i-a64-mali 30 - rockchip,rk3036-mali 31 - rockchip,rk3066-mali 32 - rockchip,rk3128-mali 33 - rockchip,rk3188-mali 34 - rockchip,rk3228-mali 35 - samsung,exynos4210-mali 36 - stericsson,db8500-mali 37 - xlnx,zynqmp-mali 38 - const: arm,mali-400 39 - items: 40 - enum: 41 - allwinner,sun50i-h5-mali 42 - amlogic,meson8-mali 43 - amlogic,meson8b-mali 44 - amlogic,meson-gxbb-mali 45 - amlogic,meson-gxl-mali 46 - hisilicon,hi6220-mali 47 - mediatek,mt7623-mali 48 - rockchip,rk3328-mali 49 - const: arm,mali-450 50 51 # "arm,mali-300" 52 53 reg: 54 maxItems: 1 55 56 interrupts: 57 minItems: 4 58 maxItems: 20 59 60 interrupt-names: 61 allOf: 62 - additionalItems: true 63 minItems: 4 64 maxItems: 20 65 items: 66 # At least enforce the first 2 interrupts 67 - const: gp 68 - const: gpmmu 69 - items: 70 # Not ideal as any order and combination are allowed 71 enum: 72 - gp # Geometry Processor interrupt 73 - gpmmu # Geometry Processor MMU interrupt 74 - pp # Pixel Processor broadcast interrupt (mali-450 only) 75 - pp0 # Pixel Processor X interrupt (X from 0 to 7) 76 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7) 77 - pp1 78 - ppmmu1 79 - pp2 80 - ppmmu2 81 - pp3 82 - ppmmu3 83 - pp4 84 - ppmmu4 85 - pp5 86 - ppmmu5 87 - pp6 88 - ppmmu6 89 - pp7 90 - ppmmu7 91 - pmu # Power Management Unit interrupt (optional) 92 - combined # stericsson,db8500-mali only 93 94 clocks: 95 maxItems: 2 96 97 clock-names: 98 items: 99 - const: bus 100 - const: core 101 102 memory-region: true 103 104 mali-supply: true 105 106 opp-table: 107 type: object 108 109 power-domains: 110 maxItems: 1 111 112 resets: 113 maxItems: 1 114 115 operating-points-v2: true 116 117 "#cooling-cells": 118 const: 2 119 120required: 121 - compatible 122 - reg 123 - interrupts 124 - interrupt-names 125 - clocks 126 - clock-names 127 128additionalProperties: false 129 130allOf: 131 - if: 132 properties: 133 compatible: 134 contains: 135 enum: 136 - allwinner,sun4i-a10-mali 137 - allwinner,sun7i-a20-mali 138 - allwinner,sun8i-r40-mali 139 - allwinner,sun50i-a64-mali 140 - allwinner,sun50i-h5-mali 141 - amlogic,meson8-mali 142 - amlogic,meson8b-mali 143 - hisilicon,hi6220-mali 144 - mediatek,mt7623-mali 145 - rockchip,rk3036-mali 146 - rockchip,rk3066-mali 147 - rockchip,rk3188-mali 148 - rockchip,rk3228-mali 149 - rockchip,rk3328-mali 150 then: 151 required: 152 - resets 153 154examples: 155 - | 156 #include <dt-bindings/interrupt-controller/irq.h> 157 #include <dt-bindings/interrupt-controller/arm-gic.h> 158 159 mali: gpu@1c40000 { 160 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 161 reg = <0x01c40000 0x10000>; 162 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-names = "gp", 170 "gpmmu", 171 "pp0", 172 "ppmmu0", 173 "pp1", 174 "ppmmu1", 175 "pmu"; 176 clocks = <&ccu 1>, <&ccu 2>; 177 clock-names = "bus", "core"; 178 resets = <&ccu 1>; 179 #cooling-cells = <2>; 180 }; 181 182... 183