xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dither.yaml (revision 3078531de10dcae44b253a35125c949ff4235284) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display dither processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display dither processor, namely DITHER, works by approximating
15  unavailable colors with available colors and by mixing and matching available
16  colors to mimic unavailable ones.
17  DITHER device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - items:
26          - const: mediatek,mt8183-disp-dither
27      - items:
28          - enum:
29              - mediatek,mt8192-disp-dither
30              - mediatek,mt8195-disp-dither
31          - enum:
32              - mediatek,mt8183-disp-dither
33
34  reg:
35    maxItems: 1
36
37  interrupts:
38    maxItems: 1
39
40  power-domains:
41    description: A phandle and PM domain specifier as defined by bindings of
42      the power controller specified by phandle. See
43      Documentation/devicetree/bindings/power/power-domain.yaml for details.
44
45  clocks:
46    items:
47      - description: DITHER Clock
48
49  mediatek,gce-client-reg:
50    description: The register of client driver can be configured by gce with
51      4 arguments defined in this property, such as phandle of gce, subsys id,
52      register offset and size. Each GCE subsys id is mapping to a client
53      defined in the header include/dt-bindings/gce/<chip>-gce.h.
54    $ref: /schemas/types.yaml#/definitions/phandle-array
55    maxItems: 1
56
57required:
58  - compatible
59  - reg
60  - interrupts
61  - power-domains
62  - clocks
63
64additionalProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/interrupt-controller/arm-gic.h>
69    #include <dt-bindings/clock/mt8183-clk.h>
70    #include <dt-bindings/power/mt8183-power.h>
71    #include <dt-bindings/gce/mt8183-gce.h>
72
73    soc {
74        #address-cells = <2>;
75        #size-cells = <2>;
76
77        dither0: dither@14012000 {
78            compatible = "mediatek,mt8183-disp-dither";
79            reg = <0 0x14012000 0 0x1000>;
80            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
81            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
82            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
83            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
84        };
85    };
86