1* Rockchip RK3228 Clock and Reset Unit 2 3The RK3228 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: should be "rockchip,rk3228-cru" 10- reg: physical base address of the controller and length of memory mapped 11 region. 12- #clock-cells: should be 1. 13- #reset-cells: should be 1. 14 15Optional Properties: 16 17- rockchip,grf: phandle to the syscon managing the "general register files" 18 If missing pll rates are not changeable, due to the missing pll lock status. 19 20Each clock is assigned an identifier and client nodes can use this identifier 21to specify the clock which they consume. All available clocks are defined as 22preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be 23used in device tree sources. Similar macros exist for the reset sources in 24these files. 25 26External clocks: 27 28There are several clocks that are generated outside the SoC. It is expected 29that they are defined using standard clock bindings with following 30clock-output-names: 31 - "xin24m" - crystal input - required, 32 - "ext_i2s" - external I2S clock - optional, 33 - "ext_gmac" - external GMAC clock - optional 34 - "ext_hsadc" - external HSADC clock - optional 35 - "phy_50m_out" - output clock of the pll in the mac phy 36 37Example: Clock controller node: 38 39 cru: cru@20000000 { 40 compatible = "rockchip,rk3228-cru"; 41 reg = <0x20000000 0x1000>; 42 rockchip,grf = <&grf>; 43 44 #clock-cells = <1>; 45 #reset-cells = <1>; 46 }; 47 48Example: UART controller node that consumes the clock generated by the clock 49 controller: 50 51 uart0: serial@10110000 { 52 compatible = "snps,dw-apb-uart"; 53 reg = <0x10110000 0x100>; 54 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 55 reg-shift = <2>; 56 reg-io-width = <4>; 57 clocks = <&cru SCLK_UART0>; 58 }; 59