xref: /freebsd/sys/contrib/device-tree/Bindings/clock/rockchip,rk3308-cru.txt (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1* Rockchip RK3308 Clock and Reset Unit
2
3The RK3308 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: CRU should be "rockchip,rk3308-cru"
10- reg: physical base address of the controller and length of memory mapped
11  region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18  If missing, pll rates are not changeable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
34   "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
35   "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
36 - "mac_clkin" - external MAC clock - optional
37
38Example: Clock controller node:
39
40	cru: clock-controller@ff500000 {
41		compatible = "rockchip,rk3308-cru";
42		reg = <0x0 0xff500000 0x0 0x1000>;
43		rockchip,grf = <&grf>;
44		#clock-cells = <1>;
45		#reset-cells = <1>;
46	};
47
48Example: UART controller node that consumes the clock generated by the clock
49  controller:
50
51	uart0: serial@ff0a0000 {
52		compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
53		reg = <0x0 0xff0a0000 0x0 0x100>;
54		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
55		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
56		clock-names = "baudclk", "apb_pclk";
57		reg-shift = <2>;
58		reg-io-width = <4>;
59		status = "disabled";
60	};
61