1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000 8 9maintainers: 10 - Taniya Das <quic_tdas@quicinc.com> 11 - Imran Shaik <quic_imrashai@quicinc.com> 12 13description: | 14 Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control 15 module which supports the clocks, resets on QDU1000 and QRU1000 16 17 See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h 18 19properties: 20 compatible: 21 enum: 22 - qcom,qdu1000-ecpricc 23 24 reg: 25 maxItems: 1 26 27 clocks: 28 items: 29 - description: Board XO source 30 - description: GPLL0 source from GCC 31 - description: GPLL1 source from GCC 32 - description: GPLL2 source from GCC 33 - description: GPLL3 source from GCC 34 - description: GPLL4 source from GCC 35 - description: GPLL5 source from GCC 36 37 '#clock-cells': 38 const: 1 39 40 '#reset-cells': 41 const: 1 42 43required: 44 - compatible 45 - reg 46 - clocks 47 - '#clock-cells' 48 - '#reset-cells' 49 50additionalProperties: false 51 52examples: 53 - | 54 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 55 #include <dt-bindings/clock/qcom,rpmh.h> 56 clock-controller@280000 { 57 compatible = "qcom,qdu1000-ecpricc"; 58 reg = <0x00280000 0x31c00>; 59 clocks = <&rpmhcc RPMH_CXO_CLK>, 60 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, 61 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, 62 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, 63 <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, 64 <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, 65 <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; 66 #clock-cells = <1>; 67 #reset-cells = <1>; 68 }; 69