1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules 8 9maintainers: 10 - A.s. Dong <aisheng.dong@nxp.com> 11 12description: | 13 i.MX7ULP Clock functions are under joint control of the System 14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC) 15 modules, and Core Mode Controller (CMC)1 blocks 16 17 The clocking scheme provides clear separation between M4 domain 18 and A7 domain. Except for a few clock sources shared between two 19 domains, such as the System Oscillator clock, the Slow IRC (SIRC), 20 and and the Fast IRC clock (FIRCLK), clock sources and clock 21 management are separated and contained within each domain. 22 23 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. 24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. 25 26 Note: this binding doc is only for A7 clock domain. 27 28 The Peripheral Clock Control (PCC) is responsible for clock selection, 29 optional division and clock gating mode for peripherals in their 30 respected power domain. 31 32 The clock consumer should specify the desired clock by having the clock 33 ID in its "clocks" phandle cell. 34 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of 35 i.MX7ULP clock IDs of each module. 36 37properties: 38 compatible: 39 enum: 40 - fsl,imx7ulp-pcc2 41 - fsl,imx7ulp-pcc3 42 43 reg: 44 maxItems: 1 45 46 '#clock-cells': 47 const: 1 48 49 clocks: 50 items: 51 - description: nic1 bus clock 52 - description: nic1 clock 53 - description: ddr clock 54 - description: apll pfd2 55 - description: apll pfd1 56 - description: apll pfd0 57 - description: usb pll 58 - description: system osc bus clock 59 - description: fast internal reference clock bus 60 - description: rtc osc 61 - description: system pll bus clock 62 63 clock-names: 64 items: 65 - const: nic1_bus_clk 66 - const: nic1_clk 67 - const: ddr_clk 68 - const: apll_pfd2 69 - const: apll_pfd1 70 - const: apll_pfd0 71 - const: upll 72 - const: sosc_bus_clk 73 - const: firc_bus_clk 74 - const: rosc 75 - const: spll_bus_clk 76 77required: 78 - compatible 79 - reg 80 - '#clock-cells' 81 - clocks 82 - clock-names 83 84additionalProperties: false 85 86examples: 87 - | 88 #include <dt-bindings/clock/imx7ulp-clock.h> 89 #include <dt-bindings/interrupt-controller/arm-gic.h> 90 91 clock-controller@403f0000 { 92 compatible = "fsl,imx7ulp-pcc2"; 93 reg = <0x403f0000 0x10000>; 94 #clock-cells = <1>; 95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 96 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 97 <&scg1 IMX7ULP_CLK_DDR_DIV>, 98 <&scg1 IMX7ULP_CLK_APLL_PFD2>, 99 <&scg1 IMX7ULP_CLK_APLL_PFD1>, 100 <&scg1 IMX7ULP_CLK_APLL_PFD0>, 101 <&scg1 IMX7ULP_CLK_UPLL>, 102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, 103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, 104 <&scg1 IMX7ULP_CLK_ROSC>, 105 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; 106 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", 107 "apll_pfd2", "apll_pfd1", "apll_pfd0", 108 "upll", "sosc_bus_clk", "firc_bus_clk", 109 "rosc", "spll_bus_clk"; 110 }; 111 112 mmc@40380000 { 113 compatible = "fsl,imx7ulp-usdhc"; 114 reg = <0x40380000 0x10000>; 115 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 117 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 118 <&pcc2 IMX7ULP_CLK_USDHC1>; 119 clock-names ="ipg", "ahb", "per"; 120 bus-width = <4>; 121 }; 122